Abstract: Nowadays, the information security has achieved a great importance, both when information is sent through a non-secure network (as the Internet) and when data are stored in massive storage devices. The cryptographic algorithms are used in order to guarantee the security of data sent or stored. A lot of research is being done in order to improve the performance of the current cryptographic algorithms, including the use of FPGAs. In this work we present an implementation of the IDEA cryptographic algorithm using reconfigurable hardware (FPGAs). In addition, in order to improve the performance of the algorithm, partial and dynamic reconfiguration has been used to implement our final circuit. This fact allows us to obtain a very high encryption speed (14.757 Gb/s), getting better results than those found in the literature.

We present a hardware implementation of population-based ant colony optimization (P-ACO) on field-programmable gate arrays (FPGAs). The ant colony optimization meta-heuristic is adopted from the natural foraging behavior of real ants and has been used to find good solutions to a wide spectrum of combinatorial optimization problems. We describe the P-ACO algorithm and present a circuit architecture that facilitates efficient FPGA implementations. The proposed design shows modest space requirements but leads to a significant reduction in runtime over software-based solutions. Several modifications and extensions of the basic algorithm are also presented, including the approximation of the heuristic function by a small, dynamically changing set of favorable decisions. © 2004 Elsevier B.V. All rights reserved. Keywords: Ant colony optimization; Ant algorithm; Field-programmable gate array; FPGA

ithm) of 0 (new algorithm) (a) Single representation (b) Double representation of 0 (c) Single representation 10 15 20 25 30 35 40 45 50 [slices] Operand size [bits] Adder-based modulo m adder Classic modulo n -1 adder New modulo 2 n -1 adder 2 RCAs and a Mux New algorithm [1] (x+y+1) mod m x y 2 Most significant bit 0 1 1 bit n+1 bits n bits 1 1 LUT (a) Classic algorithm (b) New algorithm 10 15 20 25 30 35 40 45 50 55 [slices] Operand size [bits] Adder-based modulo m adder Classic modulo 2 +1 adder New modulo 2 n +1 adder Modular Multiplication Operator for FPGAs embedding small multipliers and memory blocks [1] Unsigned multiplication and subsequent modulo Algorithm: choose such that is close to and compute ! " !# $ &%(')*,+- .+% ( //0 12% ' 3 4 576 8 9:,; > ? @$A = B2C D3:3EFHG 3I0 JKL*%(' $ &% ' )*,M% ' +N( //0 12% ' N3 JKO*% ' Efficient