In the paper an infinitesimally small segment of an interconnect has been initially considered and modeled as a two-port network which in turn allowed the modeling of a long interconnect as the cascading of several such networks. After the model order reduction by Pade-approximation various signal integrity losses, such as delay, overshoot, undershoot or glitch, etc. are estimated analytically using the reduced order interconnect model and verified through experimental simulation. Moreover, a cross-talk model, based on an aggressor and a victim, is also considered later that will be useful to analyze the behavior of signal propagation on the aggressor line in presence of inductive as well as capacitive line coupling. 1.

As technology shrinks and working frequency reaches multi gigahertz range, designing and testing interconnects are no longer trivial issues. In this paper we propose an enhanced boundary scan architecture to test high-speed interconnects for signal integrity. This architecture includes: a) a modified driving cell that generates patterns according to multiple transitions fault model; and b) an observation cell that monitors signal integrity violations. To fully comply with conventional JTAG, two new instructions are used to control cells and scan activities in the integrity test mode.

This paper aims at analysis of signal integrity for the purpose of testing high speed interconnects. This requires taking into account the effect of inputs as well as parasitic RLC elements of the interconnect. To improve the analysis/simulation time in integrity fault testing, we use reduced-order modeling that essentially performs the analysis in the frequency domain. To demonstrate the generality and usefulness of our method, we also discuss its application for test pattern generation targeting signal integrity loss.

Signal Integrity (SI) losses in the interconnects are the disturbances coming out of their distributed nature of parasitic capacitances, resistances, and inductances at high frequency operation [1]. SI losses are further aggravated if multiple interconnect lines couple energy from, or to each other. Therefore, this paper aims to analyze the cross-talk coupling effects between the two interconnects, namely the aggressor and victim lines, using the ABCD two-port network model. In order to reduce the simulation time a reduced order modeling of the interconnect line is considered. Furthermore, as stated in various literatures [7] the rising (or falling) input signal represented by a simple step function is not accurate enough, therefore in this paper the rising transitions and the falling transitions are represented more accurately using the exponential terms, and based on such input representation the time domain output signal voltage in presence of crosstalk noise, at the far end side of both aggressor line and victim line, is determined. Such output voltage representation is very helpful in estimating the delay, overshoot or undershoot etc., which are believed to cause SI losses in the SoC. 1.

As the technology is shrinking toward 50 nm and the working frequency is going into multi gigahertz range, the effect of interconnects on functionality and performance of system-on-chips is becoming dominant. More specifically, distortion (integrity loss) of signals traveling on high-speed interconnects can no longer be ignored. In this paper, we propose a new fault model, called multiple transition, and its corresponding test pattern generation mechanism. We also extend the conventional boundaryscan architecture to allow testing signal integrity in SoC interconnects. Our extended JTAG architecture collects and outputs the integrity loss information using the enhanced observation cells. The architecture fully complies with the JTAG standard and can be adopted by any SoC that is IEEE 1149.1 compliant.

At higher operating (GHz) frequency the interconnect wire does not behave like a simple metallic resistance but as a transmission line. This being the main reason for signal integrity losses in high frequency interconnect line. Signal Integrity (SI) losses in the interconnect wires are the disturbances coming out of their distributed nature of parasitic capacitances, resistances and inductances at high frequency operation. These SI losses are further aggravated if multiple interconnect lines couple energy from or to each other. In the paper two interconnect lines, as per maximal aggressor fault model [9], have been considered where the aggressor line is assumed to couple energy to the victim line only, based on which the cross-talk model of an aggressor and a victim line has been developed using ABCD two-port network model. After the model order reduction by Pade-approximation various signal integrity losses, such as delay, overshoot, undershoot or glitch etc., for a given set of applied input transitions, are estimated numerically and verified through experimental PSPICE simulation. Based on the above prediction of SI losses the applied input transitions can be identified as potential test patterns that are believed to excite the SI faults. In order to simplify the crosstalk model computation only the capacitive coupling is considered here because, inductive coupling will contribute more significantly only if the operating frequency is higher than several GHz. 1.

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single / multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling noise on the victim’s far end signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling noise introduces the delay in the victim‘s far end signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to manufacturing defect such as under-etching or even, length of the victim interconnect is increased due to improper layouts of / routings between cores and devices on chips. Influences of other interconnect parasitics on the victim´s far end signal can also be analyzed using the same model. Simulation results obtained with the proposed reduced order model is found to be quite comparable to the accuracy of the PSPICE simulation. 1.

The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC’02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects.

Abstract:- Signal integrity of high-speed interconnects has significant adverse effect on the proper function and performance of VLSI. A new crosstalk fault model is presented for testing glitch and delay in this paper. This model takes odd and even mode transmission into account based on parasitic RLC elements of interconnect. It can stimulate the maximal signal integrity loss compared to maximal aggressor (MA) model and maximal dominant signal integrity (MDSI) model. Then a compression algorithm for test space is proposed. Several properties such as symmetry, decay and superimposition are studied. Compression steps are explained in detail. Finally simulation is performed and experimental results show that this model is more effective than MA and MDSI models. Key-Words:- crosstalk, compression algorithm, fault model, high-speed interconnect 1