A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.

Injection locking characteristics of oscillators are derived and a graphical analysis is presented that describes injection pulling in time and frequency domains. An identity obtained from phase and envelope equations is used to express the requisite oscillator nonlinearity and interpret phase noise reduction. The behavior of phase-locked oscillators under injection pulling is also formulated.

This thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 µm CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 µm CMOS technology is

Abstract—This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply. Keywords—Clock and Data Recovery (CDR), 1/4-rate frequency detector (QRFD), 1/4-rate phase detector. I.

Abstract – This paper gives a performance, power and area comparison of LC vs. Ring VCOs for application to PLL designs in a standard 90 nm digital CMOS process. We develop an analytical framework for determining the best match for a high-speed clock synthesizer design based on the constraints of the application. A type-II PLL is utilized in this study because of its capability for allowing independent adjustments to the damping factor, the loop-bandwidth and loop gain.. Cadence SpectreRF is used to verify our analysis.

- Digital latches < 10 GHz

Abstract not found

As the functionality of digital chips continues to increase dramatically, chip-to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore, high speed transceiver design has be-come an important research topic. In particular, the performance of the circuits that are responsible for timing accuracy are important as bit periods continue to shrink. Furthermore, in order for these circuits to have a true impact on the performance of the system, they must use unique architectures to achieve timing accuracy rather than simply trading power consumption for performance. This thesis discusses issues related to the timing circuits on both the transmit and receive side of the link. On the transmit side, a phase-locked loop (PLL) is used to generate the clock that tells the driver when to start and stop driving the current bit onto the channel. On the receive side, a clock and data recovery (CDR) circuit is responsible for properly centering the sampling clock in the middle of the bit period. Design techniques to achieve good timing performance in both the PLL and CDR are proposed. Specifically, the PLL incorporates a supply regulated tuning scheme to combat the high levels of supply noise present in large digital chips and a resistor-based charge pump to reduce the charge pump flicker noise contribution. The CDR uses oversampling to decouple the tradeoff between two important performance metrics: jitter generation and jitter tolerance. To validate the proposed ideas, both a PLL test chip and a CDR test chip are presented. The PLL operates from 0.5GHz to 2.5GHz and achieves 2.36ps rms jitter using a ring voltage-controlled oscillator. The power consumption scales favorably with frequency, using much less power at lower frequencies where less power is needed. The CDR operates up to 3.6Gbps with a BER of less than 10-12. The measured jitter tolerance corner frequency was improved by a factor of 30 from 1MHz to 30MHz without increasing the recovered clock jitter.

The need for low-power I/Os is widely recognized, as I/Os take up a significant portion of total chip power. In recent years, researchers have pointed to the potential system-level power savings that can be realized if dynamic voltage scalable I/Os are available. However, substantial challenges remain in building such links. This paper presents the design and implementation details of opto-electronic transceiver front-end blocks where supply voltage can scale from 1.2V to 0.6V with almost linearly scalable bandwidth from 8Gb/s to 4Gb/s, and power consumption from 36mW to 5mW in a 130nm CMOS process. To the best of our knowledge, this is the first circuit demonstration of voltage-scalable optical links. It demonstrates the feasibility of dynamic voltage scalable optical I/Os.

Abstract—A 40-Gb/s transimpedance amplifier (TIA) is realized