Predicting the execution times of straight-line code sequences is a fundamental problem in the design and evaluation of hard-real-time systems. The reliability of system-level timings and schedulability analysis rests on the accuracy of execution time predictions for the basic schedulable units of work. Obtaining such predictions for contemporary microprocessors is difficult. First a summary of some of the hardware and software factors that make predicting execution time difficult is presented, along with the results of experiments that evaluate the degree of variation in execution time that may be caused by these factors. Traditional methods of measuring and predicting execution time are examined, and their strengths and weaknesses discussed. Second, we present a new technique for predicting point-to-point execution times on contemporary microprocessors. This technique is called micro-analysis. It uses machine-description rules, similar to those that have proven useful for c...

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ACL2 is a theorem proving system under development at Computational Logic, Inc., by the authors of the Boyer-Moore system, Nqthm, and its interactive enhancement, Pc-Nqthm, based on our perceptions of some of the inadequacies of Nqthm when used in large-scale verification projects. Foremost among those inadequacies is the fact that Nqthm's logic is an inefficient programming language. We now recognize that the efficiency of the logic as a programming language is of great importance because the models of microprocessors, operating systems, and languages typically constructed in verification projects must be executed to corroborate them against the realities they model. Simulation of such large scale systems stresses the logic in ways not imagined when Nqthm was designed. In addition, Nqthm does not adequately support certain proof techniques, nor does it encourage the reuse of previously developed libraries or the collaboration of semi-autonomous workers on different parts of a verifica...

We have formally specified a substantial subset of the MC68020, a widely used microprocessor built by Motorola, within the mathematical logic of the automated reasoning system Nqthm, i.e., the Boyer-Moore Theorem Prover [4]. Using this MC68020 specification, we have mechanically checked the correctness of MC68020 machine code programs for Euclid's GCD, Hoare's Quick Sort, binary search, and other well-known algorithms. The machine code for these examples was generated using the Gnu C and the Verdix Ada compilers. We have developed an extensive library of proven lemmas to facilitate automated reasoning about machine code programs. We describe a two stage methodology we use to do our machine code proofs.

Assuming the existence of garbage collection makes it easier to design implementations of concurrent data structures. However, this assumption limits their applicability. We present a methodology that, for a significant class of data structures, allows designers to first tackle the easier problem of designing a garbagecollection -dependent implementation, and then apply our methodology to achieve a garbage-collectionindependent one. Our methodology is based on the well-known reference counting technique, and employs the double compare-and-swap operation.

Previous work in software/hardware codesign has addressed issues in system modeling, partitioning, and mixed module simulation and integration. Software estimation, which provides software metrics to assist software/hardware partitioning, has not been extensively studied. In order to rapidly explore large design space encountered in software/hardware systems, automatic software estimation is indispensable in software/hardware partitioning in which designers or partitioning tools must trade off a hardware with a software implementation for the whole or a part of the system under design. In this report we present a software estimator that provides three software metrics --- execution time, program-memory size and data-memory size for a specification executing on a given processor. Experiments have shown that our estimator is fairly accurate when applied to different designs spanning from straight line code to code with branches and loops and even to hierarchical specifications. Experimen...

Assignment ImplicitAssignment Assignment PhiAssignment Jump CondJump Return The subclasses play the following roles: EmptyRegisterTransfer: used in the instruction builder to represent transfers that only set flags. See Chapter 8. RegisterTransferSet: represents sets of RegisterTransfers to be performed concurrently. Theoretically, this is a recursive structure, since it could contain an instance of itself; however, this is never allowed. Its only instance variable is transfers, an OrderedCollection of the component transfers. Call: represents procedure calls. Its instance variables are method, the Register containing the callee's address; returnValueRegister, the Register in which the result of the call will be found; and argumentLogicalRegisters, an OrderedCollection of the Registers that contain the receiver and the first two arguments. AbstractAssignment: the abstract superclass of all classes representing assignments to some storage. Its only instance variable is destinatio...

This report describes the implementation of Tornet2 station controller. The Tornet2 local area network utilizes the combination of the token ring and insertion ring network protocols. Its primary design objective is an efficient transfer of various types of data, including a real time and priority data. This report describes the operation of the Tornet2 access controller (TAC) by means of the protocol state machine diagrams with the link to real hardware signals. Overview of the hardware of the controller board and the available software is given. Also, some hints and directions for future work are presented. Contents 1 Tornet2 -- An Overview 5 1.1 Introduction : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 5 1.2 Critical Design Issues : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 6 2 State Machine Description of the TAC Controller 8 2.1 Introduction : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :...

This paper proposes a precise approach to register allocation for irregular-register architectures which is based on 0-1 integer programming (IP). Prior work shows that IP register allocation is feasible for RISC architectures, which have uniform registers and register usage. Extensions to the prior work are proposed that precisely model register irregularities including combined source/destination specifiers, memory operands, and variations in the cost of register usage. The x86 architecture is selected as a representative irregular-register architecture for experimental study. An IP register allocator is built for the x86 architecture within the Gnu C Compiler (GCC), and is compared experimentally with GCC's graph-coloring register allocator. Experimental results show that the IP allocator reduces register allocation overhead by 61% compared with the graphcoloring allocator. The results also show that the x86 IP allocator is dramatically faster than the prior RISC IP allocator, becau...

Garbage collector performance in LISP systems on custom hardware has been substantially improved by the adoption of lifetime-based garbage collection techniques. To date, however, successful lifetime-based garbage collectors have required special-purpose hardware, or at least privileged access to data structures maintained by the virtual memory system. I present here a lifetime-based garbage collector requiring no special-purpose hardware or virtual memory system support, and discuss its performance.