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BDDbased synthesis of reversible logic for large functions
 in Design Automation Conf., 2009
"... Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like lowpower design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they a ..."
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Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like lowpower design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a Binary Decision Diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding runtime and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.
Comparison of the Cost Metrics through Investigation of the Relation between Optimal NCV and Optimal NCT 3qubit Reversible Circuits
, 2006
"... A breadthfirst search method for determining optimal 3qubit circuits composed of quantum NOT, CNOT, controlledV and controlledV + (NCV) gates is introduced. Results are presented for simple gate count and for technology motivated cost metrics. The optimal NCV circuits are also compared to NCV ci ..."
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A breadthfirst search method for determining optimal 3qubit circuits composed of quantum NOT, CNOT, controlledV and controlledV + (NCV) gates is introduced. Results are presented for simple gate count and for technology motivated cost metrics. The optimal NCV circuits are also compared to NCV circuits derived from optimal NOT, CNOT and Toffoli (NCT) gate circuits. The work presented here provides basic results and motivation for continued study of the direct synthesis of NCV circuits, and establishes relations between function realizations in different circuit cost metrics. 1
Circuit integration through lattice hyperterms
"... Reducing the size of a logic circuit through lattice identities is an important and wellstudied discrete optimization problem. In this paper, we consider a related problem of integrating several circuits into a single hypercircuit using the recentlydeveloped concept of lattice hyperterms. We give ..."
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Reducing the size of a logic circuit through lattice identities is an important and wellstudied discrete optimization problem. In this paper, we consider a related problem of integrating several circuits into a single hypercircuit using the recentlydeveloped concept of lattice hyperterms. We give a combinatorial algorithm for integrating koutofn symmetrical diagrams which play important role in reliability theory. Our results show that the integration can reduce the number of circuit gates by more than twice.
SharedPPRM: A MemoryEfficient Representation for Boolean Reversible Functions
"... A memoryefficient representation scheme, sharedPPRM (SPPRM), for Boolean reversible functions is introduced and analyzed. Compared with conventional PPRM expansion, SPPRM reduces memory usages by using one memory location for many repetitive PPRM subexpressions. To evaluate the effects of data st ..."
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A memoryefficient representation scheme, sharedPPRM (SPPRM), for Boolean reversible functions is introduced and analyzed. Compared with conventional PPRM expansion, SPPRM reduces memory usages by using one memory location for many repetitive PPRM subexpressions. To evaluate the effects of data structure on SPPRM representation, two linked listbased data structures are also examined. The experimental results show the efficiency of the proposed SPPRM representation for both memory usage and CPU time.