We describe a generalized bottom up parser in which non-embedded recursive rules are handled directly by the underlying automaton, thus limiting stack activity to the activation of rules displaying embedded recursion. Our strategy is motivated by Aycock and Horspool’s approach, but uses a different automaton construction and leads to parsers that are correct for all context-free grammars, including those with hidden left recursion. The automaton features edges which directly connnect states containing reduction actions with their associated goto state: hence we call the approach reduction incorporated generalized LR parsing. Our parser constructs shared packed parse forests in a style similar to that of Tomita parsers. We give formal proofs of the correctness of our algorithm, and compare it with Tomita’s algorithm in terms of the space and time requirements of the running parsers and the size of the parsers ’ tables. Experimental results are given for standard grammars for ANSI-C, ISO-Pascal; for a non-deterministic grammar for IBM VS-COBOL, and for a small grammar that triggers asymptotic worst case behaviour in our parser. 1.

This report is the second in a two part series in which we consider a parsing technique which we call generalised recursive descent (GRD). In the first report [JS97] there is an extensive discussion of the influence of parsing techniques on language design, a full description of the GRD parsing technique, and a description of a tool, GRDP, which generates GRD parsers for suitable grammars. There are essentially two classes of GRD parsers: the full prototyping versions which are admitted by any non-left recursive grammar, and the more efficient production versions which are only guaranteed to be admitted (see below) by non-left recursive follow-determined grammars. In this report we shall consider theoretical aspects of follow-determined grammars and the languages which can be specified with them.

The size and complexity of hardware systems motivates the use of simulation for their study and analysis. Parallelization techniques are often employed to meet the memory and computational requirements for simulating large hardware designs. Furthermore, partitioning the design for parallel simulation is vital for achieving acceptable simulation throughput. This paper presents the design and implementation of a new partitioning algorithm based on a multilevel partitioning heuristic. The multilevel algorithm attempts to balance the load, maximize concurrency, and reduce inter-processor communication in three phases to improve performance of the parallel simulator. The paper presents the algorithm and reports results from of our empirical studies to compare performance of the multilevel algorithm with other partitioning techniques. A generic partitioning infrastructure was developed and integrated into the warped parallel simulation framework to ease design, implementation, and study of different partitioning algorithms. The design issues involved in the development of the generic partitioning infrastructure are discussed and the techniques employed to integrate several partitioning algorithms into this framework are also presented in the paper. The experimental results obtained from our benchmarks indicate that the multilevel algorithm yields better partitions than other partitioning algorithms included in the study.

The development of efficient parallel discrete event simulators is hampered by the large number of interrelated factors affecting performance. This problem is made more difficult by the lack of scalable representative models that can be used to analyze optimizations and isolate bottlenecks. This paper proposes a performance and scalabilty analysis framework (PSAF) for parallel discrete event simulators. PSAF is built on a platform-independent workload specification language (WSL). WSL is a language that represents simulation models using a set of fundamental performance-critical parameters. For each simulator under study, a WSL translator generates synthetic platform-specific simulation models that conform to the performance and scalability characteristics specified by the WSL description. Moreover, sets of portable simulation models that explore the effects of the different parameters, individually or collectively, on the execution performance can easily be constructed using the synthetic workload generator (SWG). The SWG automatically generates simulation workloads with different performance properties. In addition, PSAF supports the seamless integration of real simulation models into the workload specification. Thus, a benchmark with both real and synthetically generated models can be built allowing for realistic and thorough exploration of the performance space. The utility of PSAF in determining the boundaries of performance and scalability of simulation environments and models is demonstrated.

This report is the first of a two part series in which we address fundamental design issues in the syntax of programming languages and the way in which implementation difficulties have had a deleterious effect on the expresiveness of languages. We