This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-m CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB. I. INTRODUCTION V OLTAGE-CONTROLLED oscillators (VCO's) are an integral part of phas...

Rapid growth in the portable communications market has pushed designers to seek low-cost, low-power, highly integrated solutions for the RF transceiver. A number of recent efforts have concentrated on integrating many of the discrete radio receiver components in a low-cost silicon process such as CMOS [1][2]. This paper describes a prototype of a monolithic CMOS receiver that combines RF and baseband functionality by taking the carrier signal at the LNA input and producing a 10-bit digital baseband waveform. A Wide-Band Intermediate Frequency Double Conversion (WBIFDC) architecture is utilized to remove the need for external narrow-band IF filters.

In this paper the fundamental electrical limits of MOSFETs are discussed and modeled to predict the scaling limits of digital bulk CMOS circuits. Limits discussed include subthreshold leakage, short channel effects (SCE), gate induced drain leakage (GIDL), gate tunneling current, time dependent dielectric breakdown (TDDB), and hot carrier effects (HCE). This paper predicts the scaling of bulk CMOS MOSFETs for high performance microprocessors to reach its limits at drawn lengths of approximately 0:08¯m. Trends in scaling interconnects are also discussed. The device limits presented are used to project the characteristics of future processor technologies and to find scaling factors for the SPICE level 3 model parameters. A SPICE device model which can be scaled to reflect a range of MOSFET technologies from drawn lengths of 0:5¯m to 0:1¯m is presented along with a scalable wire model. Key Words and Phrases: MOSFET, device scaling, interconnect scaling, subthreshold leakage, short channel...

The use of deep submicron process technologies presents several new challenges in the area of manufacturing test. While a significant body of work has been devoted to identifying and investigating design challenges in nanometer technologies, the impact on test strategies and methodologies is still not well understood. This paper highlights the challenges to current test methodologies arising from technology driven trends, and will present an overview of emerging techniques that address deep submicron test challenges. 1.

A new technique for obtaining a DC operating point of large, hard-to-solve MOS circuits is reported in this paper. Based on homotopy, the technique relies on the provable global convergence of arc length continuation and uses a novel method for embedding the continuation parameter into MOS devices. The new embedding circumvents inefficiencies and numerical failures that limit the practical applicability of previous simpler embeddings. Use of the technique in a production environment has led to the routine solution of large, previously hard-to-solve circuits.

The aim of this work is the efficient implementation of linear continuous-time cochlear models, such as that proposed by Liu [11, 12]. The basic filter element, a transconductance-C integrator with no linearization, is evaluated in terms of dynamic range and power consumption. Linearized transconductors which employ source degeneration via single and multiple diffusors yield no net increase in current noise density, whereas linear range is improved eight and four times, respectively. Experimental results verify this improvement.

This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear principle applies immediately as long as the source-to-bulk voltages are made equal to zero (or constant). This paper addresses the conditions under which subthreshold MOS transistors still satisfy a translinear principle, but without imposing this constraint on all VBS voltages. It is found that the translinear principle results in a more general formulation than the originally found for BJT's since now multiple translinear loops can be involved. The constraint of an even number of transistors is no longer necessary. Some corollaries are stated as well and, finally, it is shown how to use the theorem for subthreshold MOS transistors operated in the ohmic regime. Index Terms---CMOS analog integrated circuits, current mode circuits, low-power circuits, nonlinear circui...

An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both obtained with this method, insight into the nonlinear operation of analog integrated circuits can be gained. For accurate distortion computations, the accuracy of the transistor models is critical. A MOS transistor model is discussed that allows us to explain the measured fourth-order nonlinear behavior of a 1-GHz CMOS upconverter. Further, the method is illustrated with several examples, including the analysis of an operational amplifier up to its gain-bandwidth product. This example has also been verified experimentally. Index Terms---Analog integrated circuits, harmonic distortion, nonlinear ...

The concept of the lumped-distributed RC notch filters in transistor-only filters domain is presented. An example of VLSI CMOS implementation of such filter is proposed. Independent tuning of real and imaginary parts of conjugate complex zeros in filter transmittance is considered. Results of SPICE simulations are shown. 1. INTRODUCTION In the 60th intensive work proceeded in the field of active filters with distributed RC lines and lumpeddistributed RC networks [1]--[12]. Unfortunately this concept has not been used in practice because of lack of control of the time-constant of distributed RC line. The active filters with distributed RC lines were discovered again by Tsividis [13], and he has named them transistor-only filters [14]. He has noticed that the enhancement MOSFET operating in the non-saturated range with VDS voltage close to zero has similar properties to uniform distributed RC line. The time-constant of the MOSFET considered as a distributed RC line can be controlled by ...

Recent papers reporting CMOS RF building blocks have aroused great expectations for RF receivers using deepsubmicron technologies. This paper examines the trend in CMOS scaling, in order to establish the required current levels and achievable performance for different feature sizes, if robust, easily manufacturable designs are to be implemented for cellular applications. The boundary conditions (system-level constraints) for such designs, in terms of the number of trimmed and untrimmed external components and the roles they play in relaxing active circuit requirements, are emphasized throughout to make comparison of active RF circuits meaningful. At 1 GHz, 0.25- m CMOS appears to be the threshold for robust, low-NF RF front ends with current consumption competitive with today's BJT implementations. Index Terms---CMOS RF, low-noise amplifier, low-power design, mixer, prescaler, RF-IC, technology scaling, wireless communication. I. INTRODUCTION S CALING of CMOS technologies has defie...