In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bit-parallel and bit-serial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field. Key words: Finite fields, polynomial basis multiplier, error detection.

Abstract. We consider a quantum polynomial-time algorithm which solves the discrete logarithm problem for points on elliptic curves over GF(2 m). We improve over earlier algorithms by constructing an efficient circuit for multiplying elements of binary finite fields and by representing elliptic curve points using a technique based on projective coordinates. The depth of our proposed implementation is O(m 2), which is an improvement over the previous bound of O(m 3). 1

Abstract- Applying the matrix-vector product idea of the Mastrovito multiplier to the GF(2 m) Montgomery multiplication algorithm, we present a new multiplier for irreducible trinomials. This multiplier and the corresponding shifted polynomial basis (SPB) multiplier have the same circuit structure for the same set of parameters. Furthermore, by establishing isomorphisms between the Montgomery and the SPB constructions of GF(2 m), we show that the Montgomery algorithm can be used to perform the SPB multiplication without any changes, and vice versa.

Abstract—This paper presents the generalized theory and an efficient graph-based technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial interpolation or matrix-based techniques and takes into consideration efficient graph-based forms which can be available as an existing resource during synthesis, verification, or simulation of digital systems. Techniques for optimization of the graph-based forms for representing the coefficients are also presented. The efficiency of the algorithm increases for larger fields. As a test case, the proposed technique has been applied to benchmark circuits over GFð2 m Þ. The experimental results show that the proposed technique can significantly speed up execution time. Index Terms—Finite or Galois fields, decision diagrams, coefficients, polynomials. Ç

Abstract. Some algorithms are more efficient than others. The complexity of an algorithm is a function describing the efficiency of the algorithm which has two measures: Space Complexity and Time Complexity. In this paper, we present complexity analysis for FPGA based designs which is based on 4-input and 1-output LUT structure followed by the majority of FPGA manufacturers. The same procedure is then applied to Karatsuba-Offman Multiplier (KOM) because of two reasons. Firstly, due to the increased use of FPGAs especially for security applications, it seems logical to compare various architectures for their efficiencies in FPGAs. Secondly, for diverse security applications, it provides a prior estimation to hardware resources and achievable timing. We consider a 4-input and 1-output structure as a basic building block available in majority of FPGAs by different FPGA manufacturers. We then compare our theoretical and experimental results for KOM in FPGAs which are fairly convincible. Key words. complexity analysis, field programmable gate arrays (FPGAs), Karatsuba-Ofman multiplier, cryptography, hardware implementations

With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults especially in sensitive and critical applications may cause serious failures and hence should be avoided. In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. New architectures are developed to detect erroneous outputs caused by certain types of faults in bit-serial polynomial basis multipliers and digit-serial normal basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults.

A new bit parallel shifted polynomial basis multiplier for GF(2 n) is presented. For some irreducible trinomials, the space complexity of the multiplier matches the best results avaliable in the literture, and its gate delay is equal to TA + ⌈log2 n ⌉ TX, where TA and TX are the delay of one 2-input AND and XOR gates, respectively. To the best of our knowledge, this is the first time that the gate delay bound TA + ⌈log2 n⌉TX is reached. For some irreducible pentanomials, its gate delay is equal to TA + (1 + ⌈log2 n⌉)TX. NIST has recommended five binary fields for the