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Fault detection architectures for field multiplication using polynomial bases
 Issue on Fault Diagnosis and Tolerance in Cryptography
, 2006
"... In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious a ..."
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Cited by 3 (3 self)
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In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. In this paper, we propose new architectures to detect erroneous outputs caused by certain types of faults in bitparallel and bitserial polynomial basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuckat faults. Although the issue of detecting soft errors in registers is not considered, the proposed schemes have the advantage that they can be used with any irreducible binary polynomial chosen to define the finite field. Key words: Finite fields, polynomial basis multiplier, error detection.
Relationship between GF(2 m) Montgomery and Shifted Polynomial Basis Multiplication Algorithms
"... Abstract Applying the matrixvector product idea of the Mastrovito multiplier to the GF(2 m) Montgomery multiplication algorithm, we present a new multiplier for irreducible trinomials. This multiplier and the corresponding shifted polynomial basis (SPB) multiplier have the same circuit structure f ..."
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Cited by 2 (1 self)
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Abstract Applying the matrixvector product idea of the Mastrovito multiplier to the GF(2 m) Montgomery multiplication algorithm, we present a new multiplier for irreducible trinomials. This multiplier and the corresponding shifted polynomial basis (SPB) multiplier have the same circuit structure for the same set of parameters. Furthermore, by establishing isomorphisms between the Montgomery and the SPB constructions of GF(2 m), we show that the Montgomery algorithm can be used to perform the SPB multiplication without any changes, and vice versa.
On the Design and Optimization of a Quantum PolynomialTime Attack on Elliptic Curve Cryptography
, 710
"... Abstract. We consider a quantum polynomialtime algorithm which solves the discrete logarithm problem for points on elliptic curves over GF(2 m). We improve over earlier algorithms by constructing an efficient circuit for multiplying elements of binary finite fields and by representing elliptic curv ..."
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Cited by 1 (0 self)
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Abstract. We consider a quantum polynomialtime algorithm which solves the discrete logarithm problem for points on elliptic curves over GF(2 m). We improve over earlier algorithms by constructing an efficient circuit for multiplying elements of binary finite fields and by representing elliptic curve points using a technique based on projective coordinates. The depth of our proposed implementation is O(m 2), which is an improvement over the previous bound of O(m 3). 1
A GraphBased Unified Technique for Computing and Representing Coefficients over Finite Fields
"... Abstract—This paper presents the generalized theory and an efficient graphbased technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial ..."
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Abstract—This paper presents the generalized theory and an efficient graphbased technique for the calculation and representation of coefficients of multivariate canonic polynomials over arbitrary finite fields in any polarity. The technique presented for computing coefficients is unlike polynomial interpolation or matrixbased techniques and takes into consideration efficient graphbased forms which can be available as an existing resource during synthesis, verification, or simulation of digital systems. Techniques for optimization of the graphbased forms for representing the coefficients are also presented. The efficiency of the algorithm increases for larger fields. As a test case, the proposed technique has been applied to benchmark circuits over GFð2 m Þ. The experimental results show that the proposed technique can significantly speed up execution time. Index Terms—Finite or Galois fields, decision diagrams, coefficients, polynomials. Ç
�2007 SWPS COMPLEXITY ANALYSIS FOR 4INPUT/1OUTPUT FPGAS APPLIED TO MULTIPLIER DESIGNS
"... Abstract. Some algorithms are more efficient than others. The complexity of an algorithm is a function describing the efficiency of the algorithm which has two measures: Space Complexity and Time Complexity. In this paper, we present complexity analysis for FPGA based designs which is based on 4inp ..."
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Abstract. Some algorithms are more efficient than others. The complexity of an algorithm is a function describing the efficiency of the algorithm which has two measures: Space Complexity and Time Complexity. In this paper, we present complexity analysis for FPGA based designs which is based on 4input and 1output LUT structure followed by the majority of FPGA manufacturers. The same procedure is then applied to KaratsubaOffman Multiplier (KOM) because of two reasons. Firstly, due to the increased use of FPGAs especially for security applications, it seems logical to compare various architectures for their efficiencies in FPGAs. Secondly, for diverse security applications, it provides a prior estimation to hardware resources and achievable timing. We consider a 4input and 1output structure as a basic building block available in majority of FPGAs by different FPGA manufacturers. We then compare our theoretical and experimental results for KOM in FPGAs which are fairly convincible. Key words. complexity analysis, field programmable gate arrays (FPGAs), KaratsubaOfman multiplier, cryptography, hardware implementations
FAULT DETECTION MULTIPLIERS IN POLYNOMIAL AND NORMAL BASIS
"... With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be mo ..."
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With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults especially in sensitive and critical applications may cause serious failures and hence should be avoided. In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. New architectures are developed to detect erroneous outputs caused by certain types of faults in bitserial polynomial basis multipliers and digitserial normal basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuckat faults.
1 Fast Bit Parallel Shifted Polynomial Basis Multipliers in GF(2 n)
"... A new bit parallel shifted polynomial basis multiplier for GF(2 n) is presented. For some irreducible trinomials, the space complexity of the multiplier matches the best results avaliable in the literture, and its gate delay is equal to TA + ⌈log2 n ⌉ TX, where TA and TX are the delay of one 2input ..."
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A new bit parallel shifted polynomial basis multiplier for GF(2 n) is presented. For some irreducible trinomials, the space complexity of the multiplier matches the best results avaliable in the literture, and its gate delay is equal to TA + ⌈log2 n ⌉ TX, where TA and TX are the delay of one 2input AND and XOR gates, respectively. To the best of our knowledge, this is the first time that the gate delay bound TA + ⌈log2 n⌉TX is reached. For some irreducible pentanomials, its gate delay is equal to TA + (1 + ⌈log2 n⌉)TX. NIST has recommended five binary fields for the
India.
"... With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be mo ..."
Abstract
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With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults especially in sensitive and critical applications may cause serious failures and hence should be avoided. In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. New architectures are developed to detect erroneous outputs caused by certain types of faults in bitserial polynomial basis multipliers and digitserial normal basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuckat faults.
GfXpress: A Technique for Synthesis and Optimization of GF(2 m) Polynomials
"... Abstract—This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m),where m is a nonzero positive integer. The technique is based on a graphbased decomposition and factorization of the polynomials, followed by efficient network factorization and optimiz ..."
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Abstract—This paper presents an efficient technique for synthesis and optimization of the polynomials over GF(2m),where m is a nonzero positive integer. The technique is based on a graphbased decomposition and factorization of the polynomials, followed by efficient network factorization and optimization. A technique for efficiently computing the coefficients of the polynomials over GF(pm),wherepis a prime number, is first presented. The coefficients are stored as polynomial graphs over GF(pm). The synthesis and optimization is initiated from this graphbased representation. The technique has been applied to minimize multipliers over the fields GF(2k),wherek=2,...,8, generated with all the 51 primitive polynomials in the 0.18µmCMOStechnology with the help of the Synopsys design compiler. It has also been applied to minimize combinational exponentiation circuits, parallel integer adders and multipliers, and other multivariate bit as well as wordlevel polynomials. The experimental results suggest that the proposed technique can reduce area, delay, and power by significant amounts. We also observed that the technique is capable of producing 100 % testable circuits for stuckat faults. Index Terms—Decision diagrams, decomposition, finite or Galois fields, polynomials, synthesis and optimization, testing, verification. I.
Transactions Briefs Concurrent Error Detection in Reed–Solomon Encoders and Decoders
"... Abstract—Reed–Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, selfchecki ..."
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Abstract—Reed–Solomon (RS) codes are widely used to identify and correct errors in transmission and storage systems. When RS codes are used for high reliable systems, the designer should also take into account the occurrence of faults in the encoder and decoder subsystems. In this paper, selfchecking RS encoder and decoder architectures are presented. The RS encoder architecture exploits some properties of the arithmetic operations in. These properties are related to the parity of the binary representation of the elements of the Galois Field. In the RS decoder, the implicit redundancy of the received codeword, under suitable assumptions explained in this paper, allows implementing concurrent error detection schemes useful for a wide range of different decoding algorithms with no intervention on the decoder architecture. Moreover, performances in terms of area and delay overhead for the proposed circuits are presented. Index Terms—Error correction coding, fault tolerance, Reed–Solomon codes. I.