The mechanization of many verification tasks relies on efficient implementations of decision procedures for fragments of first-order logic. Interactive

Word level information on the Register Transfer Level (RTL) offers information for efficient guidance of the proof process in formal verification. Therefore several proof techniques with integrated word level support from other research fields can be applied for formal verification of circuit designs as well. The focus of this work is to evaluate the proof techniques Boolean Satisfiability (SAT), SAT Modulo Theories (SMT), SWORD and Constraint Satisfaction Problem (CSP) in the context of formal hardware verification. An estimation of the effort to encode standard circuit elements is given and the advantages and disadvantages of the different encodings is studied. In our experiments we consider equivalence checking problems for circuit designs given on bit and word level. 1.

Abstract. Isabelle/HOL is a popular interactive theorem prover based on higherorder logic. It owes its success to its ease of use and powerful automation. Much of the automation is performed by external tools: The metaprover Sledgehammer relies on resolution provers and SMT solvers for its proof search, the counterexample generator Quickcheck uses the ML compiler as a fast evaluator for ground formulas, and its rival Nitpick is based on the model finder Kodkod, which performs a reduction to SAT. Together with the Isar structured proof format and a new asynchronous user interface, these tools have radically transformed the Isabelle user experience. This paper provides an overview of the main automatic proof and disproof tools. 1