Results 1 - 10
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93
Clock Distribution Networks in Synchronous Digital Integrated Circuits
- Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 82 (7 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and H-trees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of high-speed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to high-speed circuits has existed for many years. The design of the clock distribution network of certain important VLSI-based systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to high-performance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
Analysis of On-chip Inductance Effects for Distributed RLC
- Interconnects,” Trans. on Computer-Aided Design of Int. Circuits and Systems
, 2002
"... Abstract—This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ca-pacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for ..."
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Cited by 32 (6 self)
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Abstract—This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ca-pacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient perfor-mance optimization technique for distributed interconnects has been introduced. The new optimization technique has been em-ployed to analyze the impact of line inductance on the circuit be-havior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resis-tance and input capacitance with scaling can make deep submi-cron designs increasingly susceptible to inductance effects if global interconnects are not scaled. On the other hand, for scaled global interconnects with increasing line resistance per unit length, as pre-scribed by the International Technology Roadmap for Semicon-ductors, the effect of inductance on interconnect performance ac-tually diminishes. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues has also been analyzed. Index Terms—Inductance, ITRS roadmap, optimal buffering, transmission line.
Accurate Analysis of On-Chip Inductance Effects and Implications for Optimal Repeater Insertion and Technology Scaling
- PROC. SYMP. ON VLSI CIRCUITS, 2001
, 2001
"... This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the tr ..."
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Cited by 16 (5 self)
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This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Furthermore, an optimal repeater insertion scheme for distributed RLC interconnects is also presented using a novel performance optimization methodology. Additionally, the impact of line inductance on interconnect performance has been analyzed in detail with especial regards to technology scaling based on the International Technology Roadmap for Semiconductors (ITRS). Contrary to conventional wisdom, it is shown that the effect of line inductance on optimized interconnect performance will actually diminish for scaled global interconnects.
Repeater insertion in tree structured inductive interconnect
- IEEE Trans. Circuits Syst. II
, 2001
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Reduced Delay Uncertainty in High Performance Clock Distribution Networks
- PROCEEDINGS OF THE IEEE DESIGN AUTOMATION AND TEST IN EUROPE CONFERENCE
, 2003
"... The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed syn ..."
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Cited by 12 (5 self)
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The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A polynomial time algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay to the most critical data paths. Strategies for enhancing the physical layout of the clock tree to decrease delay uncertainty are also presented. Application of the methodology on benchmark circuits demonstrates clock tree topologies with decreased delay uncertainties of up to 90%. Techniques to enhance a clock tree layout have been applied on a set of benchmark circuits, yielding a reduction in delay uncertainty of up to 48%.
Managing On-chip Inductive Effects
- in IEEE TVLSI
, 2002
"... advancing steadily, chips are continuing to grow in area while crit-ical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against oth ..."
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Cited by 11 (1 self)
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advancing steadily, chips are continuing to grow in area while crit-ical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip in-ductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus struc-ture and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques. Index Terms—Crosstalk noise, delay, differential signaling, in-ductance, inductive effects, interdigitated technique. I.
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed Interconnects
- Interconnects,” Proc. of the ACM/IEEE Design Automation Conference
, 2001
"... This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behaviour and to illustra ..."
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Cited by 10 (4 self)
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This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behaviour and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in the driver capacitance and output resistance with scaling makes deep submicron (DSM) designs increasingly susceptible to inductance effects. Also, the impact of inductance variations on performance has been quantified. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues have been analyzed.
Physical modeling and system level performance characterization f a protocol processor architecture
- In Proceedings o/the 18th IEEE NORCHIP Conference
, 2000
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Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint
, 2001
"... For multiple coupled RLC nets, we formulate the min-area simultaneous shield insertion and net ordering (SINO/NB- v) problem to satisfy the given noise bound. We develop an e#cient and conservative model to compute the peak noise, and apply the noise model to a simulated-annealing (SA) based algorit ..."
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Cited by 10 (1 self)
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For multiple coupled RLC nets, we formulate the min-area simultaneous shield insertion and net ordering (SINO/NB- v) problem to satisfy the given noise bound. We develop an e#cient and conservative model to compute the peak noise, and apply the noise model to a simulated-annealing (SA) based algorithm for the SINO/NB-v problem. Extensive and accurate experiments show that the SA-based algorithm is e#cient, and always achieves solutions satisfying the given noise bound. It uses up to 71% and 30% fewer shields when compared to a greedy based shield insertion algorithm and a separated shield insertion and net ordering algorithm, respectively. To the best of our knowledge, it is the first work that presents an in-depth study on the min-area SINO problem under an explicit noise constraint.
Exploiting the on-chip inductance in high-speed clock distribution networks
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2001
"... Abstract—On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted ..."
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Cited by 9 (0 self)
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Abstract—On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits.
