Results 1  10
of
18
ABC: An Academic IndustrialStrength Verification Tool
"... Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of ..."
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Cited by 27 (13 self)
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Abstract. ABC is a publicdomain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on AndInverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.
Efficient Implementation of Property Directed Reachability
, 2010
"... the first truly new bitlevel symbolic model checking algorithm since Ken McMillan’s interpolation based model checking procedure introduced in 2003. Our experience with the algorithm suggests that it is stronger than interpolation on industrial problems, and that it is an important algorithm to stu ..."
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Cited by 6 (2 self)
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the first truly new bitlevel symbolic model checking algorithm since Ken McMillan’s interpolation based model checking procedure introduced in 2003. Our experience with the algorithm suggests that it is stronger than interpolation on industrial problems, and that it is an important algorithm to study further. In this paper, we present a simplified and faster implementation of Bradley’s procedure, and discuss our successful and unsuccessful attempts to improve it. I.
Scalable don'tcarebased logic optimization and resynthesis
 Proc. FPGA '09
"... We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reason ..."
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Cited by 4 (2 self)
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We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don’t cares computed for a window surrounding a node and can take into account external don’t cares (e.g. unreachable states). It uses a SAT solver and interpolation to find a new representation for a node. This representation can be in terms of inputs from other nodes in the window thus effecting Boolean resubstitution. Experimental results on 6input LUT networks after high effort synthesis show substantial reductions in area and delay. When applied to 20 large academic benchmarks, the LUT count and logic level is reduced by 45.0 % and 12.2%, respectively. The longest runtime for synthesis and mapping is about two minutes. When applied to a set of 14 industrial benchmarks ranging up to 83K 6LUTs, the LUT count and logic level is reduced by 11.8 % and 16.5%, respectively. Experimental results on 6input LUT networks after higheffort synthesis show substantial reductions in area and delay. The longest runtime is about 30 minutes.
Magic: An industrialstrength logic optimization, technology mapping, and formal verification tool
 Proc. IWLS'10
"... This paper presents an industrialstrength CAD system for logic optimization, technology mapping, and formal verification of synchronous designs. The new system, Magic, is based on the code of ABC that has been improved by adding industrial requirements. Distinctive features include: globalview opt ..."
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Cited by 3 (3 self)
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This paper presents an industrialstrength CAD system for logic optimization, technology mapping, and formal verification of synchronous designs. The new system, Magic, is based on the code of ABC that has been improved by adding industrial requirements. Distinctive features include: globalview optimizations for area and delay, scalable sequential synthesis, the use of whiteboxes for instances that should not be mapped, and a builtin formal verification framework to run combinational and sequential equivalence checking. Comparison against a reference industrial flow shows that Magic is capable of reducing both area and delay. Experiments on a suite of industrial FPGA designs show that LUT count is reduced by 12.7%, flipflop (FF) count is reduced by 9.4%, FFtoFF level is reduced by 22.3%, and fMAX is improved by 11.8%. A remarkable consequence of these reductions is that, although Magic itself takes time to run, the total runtime of the design flow is reduced. 1.
Recording Synthesis History for Sequential Verification
"... Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimizations are not applied because they are hard to verify. This paper develops a methodology for sequential equivalence checking ..."
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Cited by 3 (2 self)
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Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimizations are not applied because they are hard to verify. This paper develops a methodology for sequential equivalence checking using feedback from synthesis. A format for recording synthesis information is proposed. An implementation is described and experimentally compared against an efficient generalpurpose sequential equivalence checker that does not use synthesis information. Experimental results confirm expected substantial savings in runtime of equivalence checking for large designs. 1
CutBased Inductive Invariant Computation
"... This paper presents a new way of computing inductive invariants in sequential designs. The invariants are useful for strengthening inductive proofs in difficult unbounded model checking instances. The proposed computation is scalable and can flexibly trade computational effort for the expressiveness ..."
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Cited by 3 (2 self)
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This paper presents a new way of computing inductive invariants in sequential designs. The invariants are useful for strengthening inductive proofs in difficult unbounded model checking instances. The proposed computation is scalable and can flexibly trade computational effort for the expressiveness of invariants proved. Experimental results on several benchmark families show that the proposed strengthening proves many hard properties, unsolved by other model checkers. The implementation is publicly available in the synthesis and verification system ABC. Runtimes are reasonable: the hardest problem with 5K primary inputs, 3K registers, and 64K AIG nodes takes 6 minutes. 1
Combinational Techniques for Sequential Equivalence Checking”, FMCAD
, 2010
"... Often sequential logic synthesis can lead to substantially easier verification problems, compared to the generalcase for sequential equivalence checking (SEC). We prove that for a class of sequential transforms intuitively based on finite unrolling of a sequential design, SEC can be reduced to comb ..."
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Cited by 2 (2 self)
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Often sequential logic synthesis can lead to substantially easier verification problems, compared to the generalcase for sequential equivalence checking (SEC). We prove that for a class of sequential transforms intuitively based on finite unrolling of a sequential design, SEC can be reduced to combinational equivalence checking (CEC). This class includes many sequential clock gating techniques. A method based on this was applied to large industrial examples, which are problematic for a conventional SEC engine, but SEC was reduced to less than a minute in most cases with the new approach. 1
A Power Optimization Toolbox for Logic Synthesis and Mapping
"... The paper describes several complementary algorithms for poweraware logic optimization: o SimSwitch is an efficient sequential simulator for estimating switching activity of signals in large sequential designs. o PowerMap uses switching activity to make better decisions during poweraware technolog ..."
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The paper describes several complementary algorithms for poweraware logic optimization: o SimSwitch is an efficient sequential simulator for estimating switching activity of signals in large sequential designs. o PowerMap uses switching activity to make better decisions during poweraware technology mapping. o PowerDC is a resynthesis algorithm that eliminates wires with high switching activity. The proposed simulator draws on new ideas in logic representation and is geared for speed, e.g. it can simulate a 1Mnode sequential design using 1000 bit patterns for 100 cycles in about 10 seconds on a typical onecore CPU. Experiments show that, although each technique contributes to the final quality, it is their combination that gives the best results. When applied to large industrial designs in a highlyoptimized industrial flow, previous work on sequential synthesis and wireaware technology mapping led to a 27.6 % reduction in switching activity, while the techniques of this paper reduce it additionally by 19.6 % without a substantial increase in runtime or degradation of other metrics. 1
Incremental Sequential Equivalence Checking and Subgraph Isomorphism
"... A method for finding large isomorphic subgraphs in two similar circuits is proposed, and its application to sequential equivalence checking (SEC) is discussed. SEC ensures correctness of two designs. Among other things, efficient SEC is important for wider adoption of innovative sequential synthesis ..."
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Cited by 1 (0 self)
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A method for finding large isomorphic subgraphs in two similar circuits is proposed, and its application to sequential equivalence checking (SEC) is discussed. SEC ensures correctness of two designs. Among other things, efficient SEC is important for wider adoption of innovative sequential synthesis (SS) methods, which offer substantial reductions in delay, area, power and flipflop counts, compared to the traditional combinational methods. In practice, some forms of SS, such as clockgating, modify only a small portion of the design, but because of cyclic dependencies in sequential logic, current SEC solutions have to be applied to the entire designs. This leads to the inability to prove equivalence for important problems. A promising solution to SEC for such situations is to identify large isomorphic subgraphs of the two circuits. Then SEC can be proved by compositional verification. Preliminary experiments show this method can be used effectively for some difficult industrial SEC problems. The method for finding large isomorphic subgraphs is of interest in general and can be used, for example, in incremental physical design. The method is fast and effective. 1
A Toolbox for CounterExample Analysis and Optimization
"... Counterexamples are produced by formal verification engines to witness failures of safety properties. A counterexample is a sequence of input assignments bringing the design from the initial state into a state where some property fails. In practice, these input assignments contain redundancies. Thi ..."
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Counterexamples are produced by formal verification engines to witness failures of safety properties. A counterexample is a sequence of input assignments bringing the design from the initial state into a state where some property fails. In practice, these input assignments contain redundancies. This paper focuses on methods for analyzing counterexamples to detect don’tcare, optional, and essential input assignments. The proposed analysis of counterexamples helps design debugging. Additionally, it is useful to reduce the length of counterexamples derived by random simulation and for efficient refinement in localization abstraction. 1.