Abstract. ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.

This paper presents a new way of computing inductive invariants in sequential designs. The invariants are useful for strengthening inductive proofs in difficult unbounded model checking instances. The proposed computation is scalable and can flexibly trade computational effort for the expressiveness of invariants proved. Experimental results on several benchmark families show that the proposed strengthening proves many hard properties, unsolved by other model checkers. The implementation is publicly available in the synthesis and verification system ABC. Runtimes are reasonable: the hardest problem with 5K primary inputs, 3K registers, and 64K AIG nodes takes 6 minutes. 1

Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimizations are not applied because they are hard to verify. This paper develops a methodology for sequential equivalence checking using feedback from synthesis. A format for recording synthesis information is proposed. An implementation is described and experimentally compared against an efficient general-purpose sequential equivalence checker that does not use synthesis information. Experimental results confirm expected substantial savings in runtime of equivalence checking for large designs. 1

The paper describes several complementary algorithms for power-aware logic optimization: o SimSwitch is an efficient sequential simulator for estimating switching activity of signals in large sequential designs. o PowerMap uses switching activity to make better decisions during power-aware technology mapping. o PowerDC is a resynthesis algorithm that eliminates wires with high switching activity. The proposed simulator draws on new ideas in logic representation and is geared for speed, e.g. it can simulate a 1Mnode sequential design using 1000 bit patterns for 100 cycles in about 10 seconds on a typical one-core CPU. Experiments show that, although each technique contributes to the final quality, it is their combination that gives the best results. When applied to large industrial designs in a highly-optimized industrial flow, previous work on sequential synthesis and wire-aware technology mapping led to a 27.6 % reduction in switching activity, while the techniques of this paper reduce it additionally by 19.6 % without a substantial increase in runtime or degradation of other metrics. 1

This paper presents an industrial-strength CAD system for logic optimization, technology mapping, and formal verification of synchronous designs. The new system, Magic, is based on the code of ABC that has been improved by adding industrial requirements. Distinctive features include: global-view optimizations for area and delay, scalable sequential synthesis, the use of white-boxes for instances that should not be mapped, and a built-in formal verification framework to run combinational and sequential equivalence checking. Comparison against a reference industrial flow shows that Magic is capable of reducing both area and delay. Experiments on a suite of industrial FPGA designs show that LUT count is reduced by 12.7%, flip-flop (FF) count is reduced by 9.4%, FF-to-FF level is reduced by 22.3%, and fMAX is improved by 11.8%. A remarkable consequence of these reductions is that, although Magic itself takes time to run, the total runtime of the design flow is reduced. 1.

Often sequential logic synthesis can lead to substantially easier verification problems, compared to the general-case for sequential equivalence checking (SEC). We prove that for a class of sequential transforms intuitively based on finite unrolling of a sequential design, SEC can be reduced to combinational equivalence checking (CEC). This class includes many sequential clock gating techniques. A method based on this was applied to large industrial examples, which are problematic for a conventional SEC engine, but SEC was reduced to less than a minute in most cases with the new approach. 1

A method for finding large isomorphic subgraphs in two similar circuits is proposed, and its application to sequential equivalence checking (SEC) is discussed. SEC ensures correctness of two designs. Among other things, efficient SEC is important for wider adoption of innovative sequential synthesis (SS) methods, which offer substantial reductions in delay, area, power and flip-flop counts, compared to the traditional combinational methods. In practice, some forms of SS, such as clock-gating, modify only a small portion of the design, but because of cyclic dependencies in sequential logic, current SEC solutions have to be applied to the entire designs. This leads to the inability to prove equivalence for important problems. A promising solution to SEC for such situations is to identify large isomorphic subgraphs of the two circuits. Then SEC can be proved by compositional verification. Preliminary experiments show this method can be used effectively for some difficult industrial SEC problems. The method for finding large isomorphic subgraphs is of interest in general and can be used, for example, in incremental physical design. The method is fast and effective. 1

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I would like to thank my advisor Professor Sy-Yen Kuo, my committee member Dr. Kai-Hui Chang, and my mentor Dr. Szu-Chi Wang. They offered valuable guidance and taught me how to conduct solid research. In addition, they provided endless comments and advice on every paper we worked together. They taught me how to write high-quality research papers and deliver good presentations. Their guidance is essential to the final completion of this dissertation and my Ph. D. training. I also want to thank Dr. Chi-Lai Huang from Avery Design Systems for allowing me to use the company’s products in my research and supporting me to attend several international conferences. Last but certainly not the least, I would like to thank all the people who made this work possible, without their support and encouragement, I would not have pursued my Ph. D. degree.

This paper presents a framework for analyzing distribution of sequentially equivalent nodes in a hierarchical design. This information can be used for selectively collapsing hierarchical modules into 'super-modules ' resulting in improved optimization and better placement decisions. Our framework is capable of comparing any two modules in the design hierarchy in terms of logic sharing. Our current implementation is based on ABC and Verific, and we are reporting preliminary result of our experiments. 1.