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Logic Decomposition during Technology Mapping. submitted to
 IEEE Trans. CAD
, 1995
"... A problem in technology mapping is that quality of the final implementation depends significantly on the initially provided circuit structure. To resolve this problem, conventional techniques iteratively but separately apply technology independent transformations and technology mapping. In this pape ..."
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Cited by 56 (1 self)
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A problem in technology mapping is that quality of the final implementation depends significantly on the initially provided circuit structure. To resolve this problem, conventional techniques iteratively but separately apply technology independent transformations and technology mapping. In this paper, we propose a procedure which performs logic decomposition and technology mapping simultaneously. We show that the procedure effectively explores all possible algebraic decompositions. It finds an optimal tree implementation over all the circuit structures examined, while the run time is typically logarithmic in the number of decompositions. 1
On the circuit implementation problem
 IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems
, 1992
"... AbstractIn this paper, we consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, basic circuit implementation problem and the genera ..."
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Cited by 25 (0 self)
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AbstractIn this paper, we consider the problem of selecting an implementation of each circuit module from a cell library so as to satisfy overall delay and area (or delay and power) requirements. Two versions of the circuit implementation problem, basic circuit implementation problem and the general circuit implementation problem are shown to be NPhard. A pseudopolynomial time algorithm for the basic circuit implementation problem on seriesparallel circuits is developed, and heuristics for the basic circuit implementation problem on general circuits are formulated and experimented with. I.
Synthesis Methods for Field Programmable Gate Arrays
 PROCEEDINGS OF THE IEEE
, 1993
"... Field programmable gate arrays (FPGA’s) reduce the turnaround time of ..."
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Cited by 17 (0 self)
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Field programmable gate arrays (FPGA’s) reduce the turnaround time of
NonHeuristic Optimization and Synthesis of ParallelPrefix Adders
 In Proc. Int. Workshop on Logic and Architecture Synthesis
, 1996
"... The class of parallelprefix adders comprises the most areadelay efficient adder architectures  such as the ripplecarry, the carryincrement, and the carrylookahead adders  for the entire range of possible areadelay tradeoffs. The generic description of these adders as prefix structures all ..."
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Cited by 16 (6 self)
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The class of parallelprefix adders comprises the most areadelay efficient adder architectures  such as the ripplecarry, the carryincrement, and the carrylookahead adders  for the entire range of possible areadelay tradeoffs. The generic description of these adders as prefix structures allows their simple and consistent area optimization and synthesis under given timing constraints, including nonuniform input and output signal arrival times. This paper presents an efficient nonheuristic algorithm for the generation of sizeoptimal parallelprefix structures under arbitrary depth constraints. Keywords Parallelprefix adders, nonheuristic synthesis algorithm, circuit timing and area optimization, computer arithmetic, cellbased VLSI. 1 Introduction Cellbased design techniques, such as standardcells and FPGAs, together with versatile hardware synthesis are prerequisites for a high productivity in ASIC design. For the implementation of arithmetic components, the designer ...
BDDbased Logic Synthesis for LUTbased FPGAs
 DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
, 2002
"... ... This paper describes an FPGAspecific logic synthesis approach, which unites multilevel logic transformation, decomposition, and optimization techniques into a single synthesis framework. This system performs network transformation, decomposition and optimization at an early stage to generate a ..."
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Cited by 13 (1 self)
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... This paper describes an FPGAspecific logic synthesis approach, which unites multilevel logic transformation, decomposition, and optimization techniques into a single synthesis framework. This system performs network transformation, decomposition and optimization at an early stage to generate a network which can be directly mapped onto FPGAs. Our techniques are built upon a BDDbased logic decomposition system. With this system, both ANDOR decompositions and ANDXOR decompositions can be identified, resulting in large area savings for synthesized XORintensive circuits. To induce
Timing Driven Gate Duplication
 Complexity Issues and Algorithms,” ICCAD
, 2004
"... In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary ou ..."
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Cited by 10 (2 self)
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In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.
TimingDriven Logic BiDecomposition
, 2003
"... An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bidecomposition of Boolean functions and treeheight reduction of Boolean expressions. It is a technologyindependent approach that enables one to find treelike expre ..."
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Cited by 10 (0 self)
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An approach for logic decomposition that produces circuits with reduced logic depth is presented. It combines two strategies: logic bidecomposition of Boolean functions and treeheight reduction of Boolean expressions. It is a technologyindependent approach that enables one to find treelike expressions with smaller depths than the ones obtained by stateoftheart techniques. The approach can also be combined with technology mapping techniques aiming at timing optimization. Experimental results show that new points in the area/delay space can be explored, with tangible delay improvements when compared to existing techniques.
Performance optimization using exact sensitization
 In Proc. DAC
, 1994
"... A common approach to performance optimization of circuits focuses on resynthesis to reduce the length of all paths greater than the desired delay. We describe a new delay optimization procedure that optimizes only sensitizable paths greater than. Unlike previous methods that use topological analysi ..."
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Cited by 9 (2 self)
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A common approach to performance optimization of circuits focuses on resynthesis to reduce the length of all paths greater than the desired delay. We describe a new delay optimization procedure that optimizes only sensitizable paths greater than. Unlike previous methods that use topological analysis only, this method accounts for both functional and topological interactions in the circuit. Comprehensive experimental results comparing the proposed technique to a stateoftheart performance optimization procedure are presented for combinational and sequential logic circuits. 1
Timing Optimization of Logic Network Using Gate Duplication
 In Proc. Asia and South Pacific Design Automation Conference
, 1999
"... We present a timing optimization algorithm based on gate duplication. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum dela ..."
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Cited by 8 (3 self)
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We present a timing optimization algorithm based on gate duplication. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum delay reduction with the minimum duplications. The performance of the algorithm is demonstrated with experiments on benchmark circuits. Our approach can also be combined with other technologyindependent timing optimizers (such as speedup) to achieve further delay improvement. 1 Introduction Timing optimization has been an important goal in logic synthesis. In the technologyindependent phase, the internal structure of a Boolean network is restructured to obtain a logically equivalent network with the reduced maximum logic level or reduced longest path delay under a given delay model. In the technologydependent phase, technology mapping for minimum delay improves the circuit timing by selectin...
Exact Required Time Analysis via False Path Detection
 IN PROCEEDINGS OF 34TH ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 1997
"... This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into acc ..."
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Cited by 8 (6 self)
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This paper addresses how to compute required times at intermediate nodes in a combinational network given required times at primary outputs. The simplest approach is to compute them based on topological delay analysis without any consideration of false paths. In this paper, however, we take into account false paths between the intermediate nodes and the primary outputs explicitly to characterize the timing constraints at the nodes more accurately. We show that this approach leads to a technique for computing a more refined and relaxed timing constraint than that obtained by topological analysis. We generalize the notion of required times from a single constant to a relation where a signal is required at different times depending on the values of the other signals.