Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult since different paths are frequency-limiting in different parts of the multi-dimensional process space. Therefore, it is desirable to have a new diagnostic metric for robust circuit optimization. This paper presents a novel algorithm to compute the criticality probability of every edge in the timing graph of a design with linear complexity in the circuit size. Using industrial benchmarks, we verify the correctness of our criticality computation via Monte Carlo simulation. We also show that for large industrial designs with 442,000 gates, our algorithm computes all edge criticalities in less than 160 seconds.

Abstract—Architects and chip makers are worried about the impact of increasing CMOS process variability. This variability can impact a processor’s performance and, depending on how aggressively the design is pushed, its reliability. We perform the first quantitative analysis of the impact of process variability on an RTL-level specification of a microprocessor core. For each pipeline stage, we compute the expected latency, as well as the standard deviation of this latency. We show that with even modest amounts of process variability, the impact on performance can be significant, and this impact can increase when using dynamic voltage scaling. I.

Abstract — We present a new linear time technique to compute criticality information in a timing graph by dividing it into “zones”. Errors in using tightness probabilities for criticality computation are dealt with using a new clustering based pruning algorithm which greatly reduces the size of circuitlevel cutsets. Our clustering algorithm gives a 150X speedup compared to a pairwise pruning strategy in addition to ordering edges in a cutset to reduce errors due to Clark’s MAX formulation. The clustering based pruning strategy coupled with a localized sampling technique reduces errors to within 5 % of Monte Carlo simulations with large speedups in runtime. I. INTRODUCTION AND PREVIOUS WORK With scaling of technology, process parameter variations render the circuit delay as unpredictable [6], making sign-off ineffective in assuring against chip failure. Recent works concerning Statistical Static Timing Analysis (SSTA) in [1], [9] deal with this issue by treating the delay of gates and

We propose a scalable and efficient parameterized block-based statistical static timing analysis (SSTA) algorithm incorporating both Gaussian and non-Gaussian parameter distributions, capturing spatial correlations using a grid-based model. As a preprocessing step, we employ independent component analysis to transform the set of correlated non-Gaussian parameters to a basis set of parameters that are statistically independent, and principal components analysis to orthogonalize the Gaussian parameters. Given the moments of the variational parameters, we use a Padé approximation-based moment matching scheme to generate the distributions of the random variables representing the signal arrival times, and preserve correlation information by propagating arrival times in a canonical form. Our experiments reveal that for the cases, when the sensitivities of Gaussian parameters outweigh that of the non-Gaussian parameters, a Gaussian SSTA proves to be reasonably accurate. However, for the cases when the non-Gaussian parameter sensitivities dominate the Gaussians, modeling all parameters as normal leads to significant inaccuracies in the SSTA results. For both cases, our SSTA procedure is able to generate the circuit delay distributions with reasonably small prediction errors. For the ISCAS89 benchmark circuits, as compared to Monte Carlo simulations, we obtain average errors of 0.99%, 2.05%, 2.33 % and 2.36%, respectively, in the mean, standard deviation, 5 % and 95 % quantile points of the circuit delay. Experimental results show that our procedure can handle as many as 256 correlated non-Gaussian variables in about 5 minutes of run time. For a circuit with |G | gates and a layout with g spatial correlation grids, the complexity of our approach is O(g|G|). I.

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Abstract—This paper quantifies the approximation error when results obtained by Clark (Oper. Res., vol. 9, p. 145, 1961) are employed to compute the maximum (max) of Gaussian random variables, which is a fundamental operation in statistical timing. We show that a finite lookup table can be used to store these errors. Based on the error computations, approaches to different orderings for pairwise max operations on a set of Gaussians are proposed. Experimental results show accuracy improvements in the computation of the max of multiple Gaussians, in comparison to the traditional approach. In addition, we present an approach to compute the tightness probabilities of Gaussian random variables with dynamic runtime-accuracy tradeoff options. We replace required numerical computations for their estimations by closed form expressions based on Taylor series expansion that involve table lookup and a few fundamental arithmetic operations. Experimental results demonstrate an average speedup of 2 × using our approach for computing the maximum of two Gaussians, in comparison to the traditional approach, without any accuracy penalty. Index Terms—Computer-aided design (CAD), Gaussian approximation, statistical timing, very large-scale integration

Abstract—In this paper, we propose an efficient numerical algorithm for estimating the parametric yield of analog/RF circuits, considering large-scale process variations. Unlike many traditional approaches that assume normal performance distributions, the proposed approach is particularly developed to handle multiple correlated nonnormal performance distributions, thereby providing better accuracy than the traditional techniques. Starting from a set of quadratic performance models, the proposed parametric yield estimation conceptually maps multiple correlated performance constraints to a single auxiliary constraint by using a MAX operator. As such, the parametric yield is uniquely determined by the probability distribution of the auxiliary constraint and, therefore, can easily be computed. In addition, two novel numerical algorithms are derived from moment matching and statistical Taylor expansion, respectively, to facilitate efficient quadratic statistical MAX approximation. We prove that these two algorithms are mathematically equivalent if the performance distributions are normal. Our numerical examples demonstrate that the proposed algorithm provides an error reduction of 6.5 times compared to a normal-distribution-based method while achieving a runtime speedup of 10–20 times over the Monte Carlo analysis with 103 samples. Index Terms—Analog/RF circuits, MAXoperator, parametric yield.

With very large scale integrated (VLSI) circuit fabrication entering the deep sub-micron era, devices are scaled down to finer geometries, clocks are run at higher frequencies, and more functionality is integrated into one chip. All these bring a great promise of “system-on-a-chip”, but also introduce challenging new issues in the design process. As a result of the increasing frequency and density, coupling effects or crosstalk between neighboring wires are increased. These effects can cause functionality and timing failures in a circuit. The dynamic power consumption in charging or discharging coupling capacitances is timing dependent, and contributes significantly to a circuit’s power consumption. In addition, manufacturing process variations (e.g. VT, Le), and environmental variations (e.g. Vdd, Temperature) contribute to uncertainties that deeply impact the timing characteristics of a circuit. This variability makes timing verification, and consequently, timing driven circuit optimization extremely difficult. Although worst case analyses for circuit optimization are simpler, they are not desirable since they severely over-constrain the optimization problem, and result in designs that have excessive penalties in terms of area or power consumption. In this research, we investigate the essential problems of timing verification, power estimation,