Abstract—A four-stage fully differential power amplifier using a double nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and THD is-S3 dB for a 6-VP –P differential output signal at 10 kHz and a load of 50 Q. With 8-0 load and for a 10-kHz, 4-VP–P output signal, THD is-68 dB. The chip area is 0.625 mm ’ in a 1.5-~m single-poly, double-metal, n-well CMOS technology I.

Abstract—Extended-counting analog-to-digital conversion combines the accuracy of 61 modulation with the speed of algorithmic conversion. In this paper, a double-sampling technique is introduced for this type of converter. It is based on a variant of the fully floating bilinear integrator. This way, the clock frequency of the converter is almost halved. An experimental converter was designed in a 0.6- m CMOS technology for a bandwidth of 500 kHz at a 3.3-V supply. In the switched-capacitor implementation, the hardware is extensively reused. This way, the converter can be realized with only one operational amplifier. On the other hand, compared to alternative implementations, the amount of switches is increased. These are designed carefully in order not to degrade the performance. The converter converts a sample in 24 clock cycles and achieves a dynamic range of 87 dB. The peak signal-to-noise ratio (SNR) and signal-to-noise-plus-distortion ratio (SNDR) were measured to be 82 and 81 dB, respectively. The power consumption was 28-mW analog and 20-mW digital. The converter core occupies 0.7 mmP including digital logic. Index Terms—Analog-to-digital conversion, double sampling, extended counting. I.

Abstract- In this paper we discuss the design of a low-voltage (1.5V), continuous-time, biquadratic CMOS filter based on Dynamic Gate Biasing (DGB). We begin by discussing the filter’s structure and its tuning mechanism. The filter uses transconductance-C cells and implements low-pass, bandpass and highpass transfer functions. The transconductances are tuned using the gate voltages of MOSFETs operating in the triode region. We review the principle of DGB, and discuss the design of the charge pump based on the filter’s performance and tunability requirements. Circuit details of the filter elements and the charge pump are presented along with SPICE simulation results of the overall filter. I.

,4mtract — MOS technology scaling requires the use of lower supply voltages. Analog circuits operating from a low supply and achieving a sufficiently farge dynamic range must be designed if analogidigital inter-faces are to be implemented in scaled technologies. This paper describes a high-performance fifth-order low-pass switched-capacitor filter operating from a single 5-V supply. The filter uses a fully differential topology combined with input-to-output class A B amplifier design, dynamic biasing, and switched-capacitor common-mode feedback (CMFB). An experimental prototype fabricated in a 5- p m CMOS technology requires orlly 350 pW of power to meet the PCM channel filter requirements. Typical measured results are a dynamic range of 92 dB, a supply rejection (PSRR) of 40 dB over the entire Nyquist range, and a total harmonic distortion (THD) of – 73 dB for a 2-V rms dlfferentiaf output signal. The chip active area is about 3900 milz.

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