Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on probabilistic transfer matrices (PTMs). In particular, we apply them to evaluate circuit reliability in the presence of soft errors, which involves combining the PTMs of gates to form an overall circuit PTM. Information such as output probabilities, the overall probability of error, and signal observability can then be extracted from the circuit PTM. We employ algebraic decision diagrams (ADDs) to improve the efficiency of PTM operations. A particularly challenging technical problem, solved in our work, is to simultaneously extend tensor products and matrix multiplication in terms of ADDs to non-square matrices. Our PTM-based method enables accurate evaluation of reliability for moderately large circuits and can be extended by circuit partitioning. To demonstrate the power of the PTM approach, we apply it to several problems in fault-tolerant design and reliability improvement. 1

As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanoscale, devices will be prone to errors due to manufacturing defects, ageing, and transient faults. Micro-architects will be required to design their logic around defect tolerance through redundancy. However, measures of reliability must be quantified in order for such design methodologies to be acceptable. We propose a CAD framework based on probabilistic model checking which provides efficient evaluation of the reliability/redundancy trade-off for defecttolerant architectures. This framework can model probabilistic assumptions about defects, easily compute reliability figures and help designers make the right decisions. We demonstrate the power of our framework by evaluating the reliability/redundancy trade-off of a canonical example, namely NAND multiplexing. We not only find errors in analytically computed bounds published recently, but we also show how to use our framework to evaluate various facets of design trade-off for reliability. 1.

Abstract — Probabilistic model checking is a formal verification technique for analysing the reliability and performance of systems exhibiting stochastic behaviour. In this paper, we demonstrate the applicability of this approach and, in particular, the probabilistic model checking tool PRISM to the evaluation of reliability and redundancy of defect-tolerant systems in the field of computeraided design. We illustrate the technique with an example due to von Neumann, namely NAND multiplexing. We show how, having constructed a model of a defect-tolerant system incorporating probabilistic assumptions about its defects, it is straightforward to compute a range of reliability measures and investigate how they are affected by slight variations in the behaviour of the system. This allows a designer to evaluate, for example, the trade-off between redundancy and reliability in the design. We also highlight errors in analytically computed reliability bounds, recently published for the same case study. Index Terms — Probabilistic model checking, reliability, defecttolerant architectures, multiplexing

Producing reliable nanosystems requires effectively addressing the high defect densities projected for nanotechnologies. Defect avoidance methodologies based on reconfiguration offer a promising solution to achieve defect tolerance. The idea is to start by obtaining a defect map of the target nanofabric, and then configure the desired functionality ‘around ’ its defective components. In this paper, we argue for the suitability of memory-based computing nanofabrics, address the level of granularity at which defect mapping and configuration should be performed on such fabrics, and discuss the role of hierarchy towards controlling complexity. We then propose a novel group testing method to enable self-testing and self-configuration for appropriately architected memory-based nanofabrics. The proposed testing method is scalable and simple, in that it enables the entire fabric to be tested and configured using a relatively small number of easily configurable triple-module-redundancy (TMR) test tiles executing concurrently on different regions of the target nanofabric. Our experimental results demonstrate the effectiveness of the proposed method for a representative set of benchmark kernels.

As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this paper, we propose a probabilistic-based design methodology for designing nanoscale computer architectures based on Markov Random Fields (MRF). The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures based on the belief propagation algorithm. Belief propagation is a way of organizing the global computation of marginal belief in terms of smaller local computations. We will illustrate the proposed design methodology with some elementary logic examples. Figure 1: The principle of switching with carbon nanotubes. Tubes are joined by an attractive electric field. Molecular forces maintain the connection when the field is removed. (After Lieber [11]). 1.

Abstract—We present a design methodology for a nanoscale selfassembling fabrication process that uses the specificity of DNA hybridization to guide the formation of electrical circuitry. Custom design software allows us to specify the function of a structure in a way similar to that used by VLSI circuit designers. In an analogous manner to generating masks for a photolithographic process, our software generates an assembly procedure including DNA sequence allocation. We have found that the number of unique DNA sequences needed to assemble a structure scales with its surface area. Using a simple face-serial assembly order we can specify an unambiguous assembly sequence for a structure of any size with only 15 unique DNA sequences. Index Terms—Associative memories, computer architecture, DNA self-assembly, nanoelectronics, parallel processing.

In this paper we are going to explore low-level implementation issues for fault-tolerant adders based on multiplexing using majority gates (MAJ). We shall analyze the particular case of a 32-bit ripple carry adder (RCA), as well as different redundant designs using MAJ-3 (MAJ of fan-in 3) multiplexed RCAs: (i) with classical MAJ-3 gates in the restorative stages; (ii) with inverters driven by shortcircuited outputs at each restorative stage; and finally, (iii) only with short-circuited outputs at each restorative stage. From one solution to the next, the restorative MAJ-3 gates get simpler and simpler. These simplifications translate into different speeds and power consumptions; challenging aspects of future nanoelectronics. All these circuits have been designed and simulated in subthreshold. The speed and power will be reported and compared for designs in 0.18 µm as well as 70 nm (using the Berkeley Predictive Technology Model). The results reveal interesting power-speed-reliability tradeoffs. In two of these designs, depending on the way the MAJ-3 function is implemented, defects translate into increased power, and suggest a (simple) way of detecting them. A detection circuit can trigger reconfiguration at a higher level, leading to a seamless transition from a fault-tolerant circuit to a defecttolerant system. The main advantage of such an approach would be that reconfiguration could be done on-line, i.e., while the circuit is still operating correctly.

Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fault tolerance embedded so as to satisfy the fundamental requirement of computational correctness. In this paper an architectural-level computation model is proposed for fault tolerant computations in nanoelectronic processors. The proposed scheme is capable of guaranteeing the correctness of each instruction through exploitation of both hardware and time redundancy, even under high and variable fault rates. Each instruction is confirmed by multiple computation instances. Through a speculative execution based on unconfirmed results, the proposed scheme eliminates the severe performance deterioration typically caused by time redundancy approaches on data dependent instructions. To avoid the exponential growth of resource allocation introduced by the hardware redundancy approaches on the speculations, a hardware allocation framework is developed in the proposed scheme to control the growth of hardware resources while preserving the low latency achieved through the speculative executions. We set up an experimental framework to validate the effectiveness of the proposed scheme as well as to investigate multiple tradeoff points within the proposed approach. Experimental data further confirm that the proposed approach achieves the goal of providing fault tolerance in the pipelined nanoelectronic processors, while at the same time providing high system performance and efficient utilization of hardware resources.

As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research priority. It is expected that nanoarchitectures will confront devices and interconnections with high inherent defect rates, which motivates the search for new architectural paradigms. In this chapter, we exam probabilistic-based design methodologies for designing nanoscale computer architectures based on Markov Random Fields (MRF) The MRF can express arbitrary logic circuits and logic operation is achieved by maximizing the probability of state configurations in the logic network. Maximizing state probability is equivalent to minimizing a form of energy that depends on neighboring nodes in the network. Once we develop a library of elementary logic components, we can link them together to build desired architectures. Overall, the probabilistic-based design can dynamically adapt to structural and signal-based faults.

Abstract. The structure and operation of multi-cellular organisms relies, among other things, on the specialization of the cells ’ physical structure to a finite set of specific operations. If we wish to make the analogy between a biological cell and a digital processor, we should note that nature’s approach to parallel processing is subtly different from conventional von Neumann architectures or even from conventional parallel processing approaches, where specialization is obtained by adapting software to a fixed hardware structure. In this article we will present the outline of a novel processor architecture based on the Move or TTA (Transport-Triggered Architecture) approach. The features of such architectures allow them to implement systems that more closely resemble, within the limitations imposed by the capabilities of conventional silicon, the general modus operandi of multi-cellular organisms. 1