Embedded processors for Systems-on-Chip o#er unique possibilities to increase the performance under tight cost budgets. One such possibility, recently o#ered by many commercial processors, is the extension of the instruction set for a specific application---that is, the introduction of customised functional units. It is essential, both to limit cost and risk in the design process and to explore appropriately the design space, to develop algorithms that decide automatically from high-level application code which operations are to be carried out in customised functional units. A few algorithms exists but are severely limited in the type of operation clusters they can choose and hence reduce significantly the e#ectiveness of specialisation. In this paper we introduce a more general algorithm which selects maximalspeedup convex subgraphs of the application dataflow graph under fundamental microarchitectural constraints. We show that our algorithm is an essential component for the successful exploitation of the specialisation potentials and that the hardware cost incurred to specialise the processor is moderate when compared to its e#ectiveness.