This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC---a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language co...

An instruction set serves as the interface between hardware and software in a computer system. In an application specific environment, the system per-formance can be improved by designing an instruction set that matches the characteristics of hardware and the application. We present a systematic approach to generate application-specific instruction sets so that software applications can be efficiently mapped to a given pipelined microarchitec-ture. The approach synthesizes instruction sets from application bench-marks, given a machine model, an objective function, and a set of design constraints. In addition, assembly code is generated to show how the benchmarks can be compiled with the synthesized instruction set. The problem of designing instruction sets is formulated as a modified schedul-ing problem. A binary tuple is proposed to model the semantics of instruc-tions and integrate the instruction formation process into the scheduling process. A simulated annealing scheme is used to solve for the schedules. Experiments have shown that the approach is capable of synthesizing pow-erful instructions for modern pipelined micro-processors, and running with reasonable time and a modest amount of memory for large applications.

Current processors are programmed through a fixed interface called the Instruction Set Architecture (ISA). Consequently, a compiler targeting such a processor is forced to choose instructions from the provided instruction set while generating code for a given application. Often this instruction set is not a suitable match for the computational requirements of the application program. With in this context, we ask ourselves the following questions. 1. Can application performance be improved if the compiler had the freedom to pick the instruction set on a per application basis? 2. Can we build cost-effective processors that provide the ability to efficiently emulate compiler determined instruction sets and yet are not application specific? 3. Given that the desired processor capabilities are feasible, can the compiler determine an optimal set of instructions for a given application and generate code that can effectively exploit the processor capabilities? In this thesis, we provide sufficient evidence to answer these questions in the affirmative. Through a combination of architectural innovations and novel compilation techniques, this dissertation demonstrates that it is possible to attain significant improvement in performance, up to an order of magnitude in some cases, on general purpose and multimedia applications over comparable fixed ISA processors. We propose classes of microprocessors that allow application programs to add and subtract functional units yielding a dynamically varying instruction set interface to the running application without compromising current compatibility model. First half of this dissertation describes this novel class of architectures, focusing on a specific subclass called Adaptive Explicitly Parallel Instruction Computing (AEPIC) architectures...

Introduction Mobile and personal communication systems, and multi-media are among the most prominently growing sectors of the electronics industry today. As an illustration, Figure 1 gives an indication of the volume of some personal communication applications in the European market. New business and home applications are emerging, using advanced communication media such as satellite links, cellular radio, or high-speed optical networks. The success of these developments will however depend to a great extent on the ability to realise complex digital signal processing functionalities in cost-efficient VLSI chips. 1990 1992 1994 1996 40 30 20 10 0 Million users Cordless Cellular Paging Private mobile Figure 1. European market of personal communication systems (source : Elsevier Advanced Technology). The design of these chips is subject to stringent requirements in terms of processing performance and power dissipation. At the same

The design of an instruction set processor includes several related design tasks: instruction set design, microarchitecture design, and code generation. Although there have been automatic approaches for each individual task, the investigation of the interaction between these tasks still primarily relies on designers' experience and ingenuity. It is thus the goal of this research to develop formal models and algorithms to investigate such interaction systematically. This dissertation presents a two-phase co-synthesis approach to the problem. In the architectural level, given a set of application benchmarks and a pipeline structure, the ASIA (Automatic Synthesis of Instruction set Architecture) design automation system generates an instruction set and allocates hardware resources which best fit the applications, and, at the same time, maps the applications to assembly code with the synthesized instruction set. This approach formulates the codesign problem as a modified scheduling/allocat...

Machine (WAM) [36]. Their instruction sets were derived from the WAM to support execution of Prolog programs. These processors are special purpose, microcoded engines that depend on parallel execution of operations within each relatively coarsegrained instruction for high performance. Initial designs implemented only the instructions that supported the WAM and depended on a host processor for nonWAM computations. To support Prolog built-ins (primitive Prolog operations provided by the system) and system I/O, newer designs incorporate general purpose instructions to minimize dependence on a host. Alternatively, the use of a simple, non-WAM instruction set better supports compiler optimization. Several such special purpose reduced instruction set architectures have been proposed for logic programming [11, 18, 19, 24]. These architectures include primitives that support the use of tagged data, pointer dereference, and multi-waybranches. Our hypothesis is that providing support for both co...