Results 1  10
of
11
Nearly optimal register allocation with PBQP
 In Proceedings of the 7th Joint Modular Languages Conference (JMLC’06). LNCS
, 2006
"... Abstract. For irregular architectures global register allocation remains a challenging problem, and has received a lot of attention in recent years. The classical graphcolouring analogy used by Chaitin and Briggs is not adequate for irregular architectures featuring nonorthogonal instruction sets ..."
Abstract

Cited by 6 (1 self)
 Add to MetaCart
(Show Context)
Abstract. For irregular architectures global register allocation remains a challenging problem, and has received a lot of attention in recent years. The classical graphcolouring analogy used by Chaitin and Briggs is not adequate for irregular architectures featuring nonorthogonal instruction sets and irregular register sets. Previous work [1, 2] on register allocation based on partitioned boolean quadratic programming (PBQP) has demonstrated that this approach is effective for highly irregular architectures and small benchmarks. However, experiments have shown that the heuristic used for nonreducible nodes performs poorly for larger benchmarks and more regular architectures. In this paper we present a new heuristic for PBQP, which significantly outperforms the old heuristic, and produces register allocations equal to those of the stateoftheart graphcolouring approach. We also present a new solver for PBQP which is based on branchandbound and is able to solve register allocations optimally. The branchandbound solver allows PBQP to be used as a progressive register allocator, where programmers may explicitly trade extra compile time for a better register allocation. Experiments were conducted using the register allocation problems in the SPEC2000 benchmark suite as input, with IA32 as the target architecture. Using an optimal solver for PBQP we were able to solve 97.4 % of the register allocation problems in SPEC2000 optimally. 1
Instruction selection by graph transformation
, 2010
"... Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome this limitation, we are the first to employ graph transformation, the natural generalization of tree rewriting. Current ..."
Abstract

Cited by 3 (2 self)
 Add to MetaCart
(Show Context)
Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome this limitation, we are the first to employ graph transformation, the natural generalization of tree rewriting. Currently, the only approach allowing us to pair graphbased instruction selection with linear time complexity is the mapping to the Partitioned Boolean Quadratic Problem (PBQP). We present formal foundations to verify this approach and therewith identify two problems of the common method and resolve them. We confirm the capabilities of PBQPbased instruction selection by a comparison with a finelytuned handwritten instruction selection.
An analysis of graph coloring register allocation
, 2006
"... Graph coloring is the de facto standard technique for register allocation within a compiler. In this paper we examine the importance of the quality of the coloring algorithm and various extensions of the basic graph coloring technique by replacing the coloring phase of the GNU compiler’s register al ..."
Abstract

Cited by 2 (1 self)
 Add to MetaCart
(Show Context)
Graph coloring is the de facto standard technique for register allocation within a compiler. In this paper we examine the importance of the quality of the coloring algorithm and various extensions of the basic graph coloring technique by replacing the coloring phase of the GNU compiler’s register allocator with an optimal coloring algorithm. We then extend this optimal algorithm to incorporate various extensions such as coalescing and preferential register assignment. We find that using an optimal coloring algorithm has surprisingly little benefit and empirically demonstrate the benefit of the various extensions.
Register Allocation Algorithms
"... Register allocation is the process of multiplexing a huge number of target program variables onto a small number of on chip registers. And the ultimate goal is to keep as many operands as possible in registers to minimize the communications between memory and CPU, and in the meantime, maximize the e ..."
Abstract
 Add to MetaCart
Register allocation is the process of multiplexing a huge number of target program variables onto a small number of on chip registers. And the ultimate goal is to keep as many operands as possible in registers to minimize the communications between memory and CPU, and in the meantime, maximize the execution speed of program execution. Register allocation is a well known NPcomplete problem. Even though plenty of efforts have been dedicated to register allocation, there are still a lot of challenging problems facing concurrent compiler scientists; this paper is aimed to provide a general survey on present register allocation algorithms and analyze the main perplexing issues and their possible solutions. Mainly the following are the register allocation algorithm topics we have been
Register Loading via Linear Programming
, 2012
"... We study the following optimization problem. The input is a number k and a directed graph with a specified “start ” vertex, each of whose vertices may have one “memory bank requirement”, an integer. There are k “registers”, labeled 1...k. A valid solution associates to the vertices with no bank requ ..."
Abstract
 Add to MetaCart
(Show Context)
We study the following optimization problem. The input is a number k and a directed graph with a specified “start ” vertex, each of whose vertices may have one “memory bank requirement”, an integer. There are k “registers”, labeled 1...k. A valid solution associates to the vertices with no bank requirement one or more “load instructions ” L[b,j], for bank b and register j, such that every directed trail from the start vertex to some vertex with bank requirement c contains a vertex u that has been associated L[c,i] (for some register i ≤ k) and no vertex following u in the trail has been associated an L[b,i], for any other bank b. The objective is to minimize the total number of associated load instructions. We give a k(k +1)approximation algorithm based on linear programming rounding, with (k+1) being the best possible unless Vertex Cover has approximation 2−ǫ for ǫ> 0. We also present a O(klogn) approximation, with n being the number of vertices in the input directed graph. Based on the same linear program, another rounding method outputs a valid solution with objective at most 2k times the optimum for k registers, using 2k−1 registers. 1
What’s Wrong with Graph Coloring?
"... Graph coloring is the de facto standard technique for register allocation within a compiler. In this paper we examine the intuition that a better coloring algorithm results in better register allocation. By replacing the coloring phase of thegcc compiler’s register allocator with an optimal coloring ..."
Abstract
 Add to MetaCart
(Show Context)
Graph coloring is the de facto standard technique for register allocation within a compiler. In this paper we examine the intuition that a better coloring algorithm results in better register allocation. By replacing the coloring phase of thegcc compiler’s register allocator with an optimal coloring algorithm, we demonstrate both the importance of extending the graph coloring model to better express the costs of allocation decisions and the unsuitability of a pure graph coloring model of register allocation. 1
Thesis Proposal Towards a More Principled Compiler: Progressive Backend Compiler Optimization
, 2006
"... As we reach the limits of processor performance and architectural complexity increases, more principled approaches to compiler optimization are necessary to fully exploit the performance potential of modern architectures. Existing compiler optimizations are typically heuristicdriven and lack a deta ..."
Abstract
 Add to MetaCart
(Show Context)
As we reach the limits of processor performance and architectural complexity increases, more principled approaches to compiler optimization are necessary to fully exploit the performance potential of modern architectures. Existing compiler optimizations are typically heuristicdriven and lack a detailed model of the target architecture. In this proposal I develop the beginnings of a framework for a principled backend optimizer. Ideally, a principled compiler would consist of tightly integrated, locally optimal, optimization passes which explicitly and exactly model and optimize for the target architecture. Towards this end this proposal investigates two pivotal backend optimizations: register allocation and instruction selection. I propose to tightly integrate these optimizations in an expressive model which can be solved progressively, approaching optimality as more time is allowed for compilation. I present an expressive model for register allocation based on multicommodity network flow that explicitly captures the important components of register allocation
Register Coalescing Techniques for Heterogeneous Register Architecture with Copy Sifting
"... Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register file ..."
Abstract
 Add to MetaCart
Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register file. Although this register architecture is still common in most generalpurpose processors, embedded processors often contain heterogeneous registers, which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we show that optimistic coalescing is also useful for an embedded processor to better handle such heterogeneity of the register architecture, and developed a modified algorithm for optimal coalescing that helps a register allocator. In the experiment, an existing register allocator was able to achieve up to 13.0 % reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.
A Global Progressive Register Allocator
, 2006
"... This paper describes a global progressive register allocator, a register allocator that uses an expressive model of the register allocation problem to quickly find a good allocation and then progressively find better allocations until a provably optimal solution is found or a preset time limit is re ..."
Abstract
 Add to MetaCart
(Show Context)
This paper describes a global progressive register allocator, a register allocator that uses an expressive model of the register allocation problem to quickly find a good allocation and then progressively find better allocations until a provably optimal solution is found or a preset time limit is reached. The key contributions of this paper are an expressive model of global register allocation based on multicommodity network flows that explicitly represents spill code optimization, register preferences, copy insertion, and constant rematerialization; two fast, but effective, heuristic allocators based on this model; and a more elaborate progressive allocator that uses Lagrangian relaxation to compute the optimality of its allocations. Our progressive allocator demonstrates code size improvements as large as 16.75 % compared to a traditional graph allocator. On average, we observe an initial improvement of 3.47%, which increases progressively to 6.84 % as more time is permitted for compilation.