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65
Test pattern generation using Boolean satisfiability
 IEEE Transactions on ComputerAided Design
, 1992
"... AbstractThis article describes the Boolean satisfiability method for generating test patterns for single stuckat faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted and faulted ..."
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Cited by 256 (15 self)
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AbstractThis article describes the Boolean satisfiability method for generating test patterns for single stuckat faults in combinational circuits. This new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean diference between the unfaulted and faulted circuits. Second, it applies a Boolean satisjiability algorithm to the resulting formula. This approach differs from previous methods now in use, which search the circuit structure directly instead of constructing a formula from it. The new method is general and effective: it allows for the addition of heuristics used by structural search methods, and it has produced excellent results on popular test pattern generation benchmarks. I.
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
 IEEE Transactions on Computers
, 1981
"... The DAlgorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement Error Correction and Translation (ECAT) functions. PODEM (PathOriented Decision Making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implic ..."
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Cited by 220 (0 self)
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The DAlgorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement Error Correction and Translation (ECAT) functions. PODEM (PathOriented Decision Making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0 1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALC over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the DAlgorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.
Constraint satisfaction using constraint logic programming
 Artificial Intelligence
, 1992
"... Constraint logic programming (CLP) is a new class of declarative programming languages whose primitive operations are based on constraints (e.g. constraint solving and constraint entailment). CLP languages naturally combine constraint propagation with nondeterministic choices. As a consequence, the ..."
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Cited by 75 (3 self)
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Constraint logic programming (CLP) is a new class of declarative programming languages whose primitive operations are based on constraints (e.g. constraint solving and constraint entailment). CLP languages naturally combine constraint propagation with nondeterministic choices. As a consequence, they are particularly appropriate for solving a variety of combinatorial search problems, using the global search paradigm, with short development time and efficiency comparable to procedural tools based on the same approach. In this paper, we describe how the CLP language cc(FD), a successor of CHIP using consistency techniques over finite domains, can be used to solve two practical applications: testpattern generation and car sequencing. For both applications, we present the cc(FD) program, describe how constraint solving is performed, report experimental results, and compare the approach with existing tools.
MultiLevel Logic Optimization by Implication Analysis
 In International Conference on Computer Aided Design
, 1994
"... This paper proposes a new approach to multilevel logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPGbased methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATP ..."
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Cited by 50 (7 self)
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This paper proposes a new approach to multilevel logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPGbased methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPGbased method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C'. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are "good" candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive "good" Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS85 benchmark circuits our tool HANNI...
OCCOM: Efficient Computation of ObservabilityBased Code Coverage Metrics for Functional Verification
, 1998
"... Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the de ..."
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Cited by 46 (2 self)
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Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Coverage metrics proposed for measuring the extent of design verification provided by a set of functional simulation vectors should compute statement execution counts (controllability information) , and check to see whether effects of possible errors activated by program stimuli can be observed at the circuit outputs (observability information). Unfortunately, the metrics proposed thus far, either do not compute both types of information, or are inefficient, i.e., the overhead of computing the metric is very large. In this paper, we provide the details of an efficient method to compute an Observabilitybased Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs. This method offers a more accurate assessment of design verification coverage than line coverage, and is significantly more computationally efficient than prior efforts to assess observability information because it breaks up the computation into two phases: Functional simulation of a modified HDL model, followed by analysis of a flowgraph extracted from the HDL model. Commercial HDL simulators can be directly used for the timeconsuming first phase, and the second phase can be performed efficiently using concurrent evaluation techniques.
Efficient Generation of Test Patterns Using Boolean Satisfiability
 IEEE Trans. on CAD
, 1990
"... A combinational circuit can be tested for the presence of a single stuckat fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of a ..."
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Cited by 40 (4 self)
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A combinational circuit can be tested for the presence of a single stuckat fault by applying a set of inputs that excite a verifiable output response in that circuit. If the fault is present, the output will be different than it would be if the fault were not present. Given a circuit, the goal of an automatic test pattern generation system is to generate a set of input sets that will detect every possible single stuckat fault in the circuit. This dissertation describes a new method for generating test patterns: the Boolean satisfiability method. The new method generates test patterns in two steps: First, it constructs a formula expressing the Boolean difference between the unfaulted and faulted circuits. Second, it applies a Boolean satisfiability algorithm to the resulting formula. This approach differs from most programs now in use, which directly search the circuit data structure instead of constructing a formula from it. The new method is quite general and allows for the additio...
Computation of Floating Mode Delay in Combinational Circuits: Theory and Algorithms
 IEEE TRANSACTIONS ON CAD
, 1993
"... This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologic ..."
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Cited by 34 (1 self)
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This paper addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at5 the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it cannot propagate an event. Thus, the true delay corresponds to the length of the longest true path. This forces us to examine the conditions under which a path is true. We introduce the notion of static cosensitization of paths which leads us to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. We apply these results to develop a delay computation algorithm that has the unique feature that it is able to determine the truth or falsity of entire sets of paths simultaneously. This algorithm uses conventional stuckatfault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits.
Logic optimization and equivalence checking by implication analysis
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 1997
"... Abstract — This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this appr ..."
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Cited by 21 (0 self)
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Abstract — This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effective heuristics are presented to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good ” candidates for the minimization of the circuit. A main advantage of the proposed approach is that it operates directly on the structural netlist description of the circuit so that the technical consequences of the performed transformations can be evaluated in an easy way, permitting better control of the optimization process with respect to the specific goals of the designer. Therefore, the presented technique can serve as a basis for optimization techniques targeting nonconventional design goals. This has already been shown for random pattern testability [11] and lowpower consumption [28]. This paper only considers area minimization, and our experimental results show that the method presented is competitive with conventional technologyindependent minimization techniques. For many benchmark circuits, our tool Hannover implication tool based on learning (HANNIBAL) achieves the best minimization results published to date. Furthermore, the optimization approach presented is shown to be useful in formal verification. Experimental results show that our optimizationbased verification technique works robustly for practical verification problems on industrial designs. Index Terms—ATPG, implication analysis, logic synthesis, logic verification, miter, permissible function, recursive learning, redundancy elimination, transduction. I.
Fast Postplacement Rewiring Using Easily Detectable Functional Symmetries
 IN DESIGN AUTOMATION CONFERENCE
, 2000
"... Timing convergence problem arises when the estimations made during logic synthesis can not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement ..."
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Cited by 15 (3 self)
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Timing convergence problem arises when the estimations made during logic synthesis can not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear time algorithm is proposed to detect functional symmetries in the Boolean network and is used as the basis for rewiring. Integration with an existing gate sizing algorithm further proves the effectiveness of our technique. Experimental results are very promising.
A Parallel Branch And Bound Algorithm For Test Generation
 IEEE Transactions on Computer Aided Design
, 1989
"... For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hardtodetect (HTD) faults which might remain undetected even after a large number of backtracks. We identify the problems inherent in a uniprocessor implementation of a test generation algorit ..."
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Cited by 15 (3 self)
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For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hardtodetect (HTD) faults which might remain undetected even after a large number of backtracks. We identify the problems inherent in a uniprocessor implementation of a test generation algorithm and propose a parallel test generation algorithm which tries to achieve a high fault coverage for HTD faults in a reasonable amount of time. A dynamic search space allocation strategy is used which ensures that the search spaces allocated to different processors are disjoint. The parallel test generation algorithm has been implemented on an Intel iPSC/2 hypercube. Results are presented using the ISCAS combinational benchmark circuits which conclusively prove that parallel processing of HTD faults does indeed result in high fault coverage which is otherwise not achievable by a uniprocessor algorithm in limited CPU time. The parallel algorithm exhibits superlinear speedups in some cases due...