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Digital Background Correction of Harmonic Distortion in Pipelined ADCs
 Circuits and System I: Regular Papers, IEEE Transactions on
, 2006
"... Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dom ..."
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Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in highresolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in highaccuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs. Index Terms—Analogtodigital conversion, calibration, harmonic distortion, mixed analog–digital integrated circuits (ICs).
PhaseNoise Cancellation Design Tradeoffs in DeltaSigma FractionalN PLLs
 IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing
, 2003
"... Abstract—A theoretical analysis of a recently proposed phasenoise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in 16 fractional phasedlocked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop ..."
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Abstract—A theoretical analysis of a recently proposed phasenoise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in 16 fractional phasedlocked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop bandwidth that can be achieved by PLLs incorporating the technique are quantified. Design guidelines are derived that enable customization of the technique in terms of PLL target specifications. Index Terms—Delta–sigma modulator, fractional PLL, phasedlocked loop (PLL), segmented digitaltoanalog converter (DAC), synthesizer. I.
Quadrature Mismatch Shaping for DigitaltoAnalog Converters
"... Abstract—Quadrature sigma–delta analogtodigital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digitaltoanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise i ..."
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Abstract—Quadrature sigma–delta analogtodigital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digitaltoanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to nearperfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the wellknown butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient firstorder QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance. Index Terms—Butterfly shuffler, mismatch shaping, quadrature bandpass (QBP), treestructured, 61 analogtodigital converters (ADCs). I.
Multibit Quadrature SigmaDelta Modulator with DEM Scheme
 in IEEE International Symposium on Circuits and Systems, ISCAS
, 2004
"... A simple dynamic element matching (DEM) scheme for sampled data systems is presented. The scheme is suitable for SwitchCapacitor (SC) or SwitchCurrent circuits. The DEM scheme eliminates the mirror spectral image around +/Fs/4, where Fs is the sampling frequency, while generally introducing a mor ..."
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Cited by 3 (0 self)
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A simple dynamic element matching (DEM) scheme for sampled data systems is presented. The scheme is suitable for SwitchCapacitor (SC) or SwitchCurrent circuits. The DEM scheme eliminates the mirror spectral image around +/Fs/4, where Fs is the sampling frequency, while generally introducing a more benign selfimage. The scheme is suitable for quadrature SC BandPass (BP) Σ∆ modulators with a centre frequency at Fs/4 orFs/4, where it can minimize the quantization noise mirror image and where the signal mirror image can be suppressed. Furthermore, a quadrature mismatch noise shaping method that can be used with this DEM scheme is introduced. 1.
A tight signalband power bound on mismatch noise in a mismatch shaping digitaltoanalog converter
 IEEE Trans. Inf. Theory
, 2004
"... Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its ..."
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Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signaltonoise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatchshaping DACs exploit builtin redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatchshaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatchshaping DAC: the dithered firstorder lowpass treestructured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dcfree sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signalband DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analogtodigital, data converters, dcfree sequences, delta–sigma (16), digitaltoanalog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.
LSB Dithering in MASH Delta–Sigma D/A Converters
"... Abstract—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can ..."
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Abstract—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither’s contribution to the power spectral density of the multistage digital 16 modulator’s output. A large class of popular multistage digital 16 modulators that satisfy the conditions are identified and tabulated for easy reference. Index Terms—Delta–sigma (16) modulation, dither techniques, MASH, quantization. I.
Quadrature Mismatch Shaping with a Complex, Tree Structured DAC
 in IEEE International Symposium on Circuits and Systems, ISCAS
, 2006
"... Abstract — Quadrature Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. If two separated multibit feedback DACs are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an unbalance between the I ..."
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Abstract — Quadrature Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. If two separated multibit feedback DACs are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an unbalance between the I and Q DAC. This paper proposes a new quadrature bandpass mismatch shaping technique. In our approach the I and Q DACs are merged into one complex DAC, which leads to nearperfect I/Q balance. To select the unit DAC elements of the complex, multibit DAC, the wellknown tree structured element selection logic is generalized toward a complex structure and necessary conditions for its correct operation are derived. Finally, a very efficient firstorder quadrature shaper implementation is proposed and simulations show the effectiveness of the quadrature bandpass mismatch shaping technique. I.
Author manuscript, published in "IEEE 19th European Conference on Circuit Theory and Design (ECCDT'09), Antalya: Turkey (2009)"
, 2010
"... Completely first order and tone free partitioned data weighted averaging technique used in a multibit delta sigma modulator ..."
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Completely first order and tone free partitioned data weighted averaging technique used in a multibit delta sigma modulator