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Necessary and sufficient conditions for mismatch shaping in a gernal class of multi-bit DACs (2002)

by J Welz, I Galton
Venue:IEEE Trans. Circuits Syst. II
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Digital Background Correction of Harmonic Distortion in Pipelined ADCs

by Andrea Panigada, Student Member, Ian Galton - Circuits and System I: Regular Papers, IEEE Transactions on , 2006
"... Abstract—Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dom ..."
Abstract - Cited by 5 (1 self) - Add to MetaCart
Abstract—Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in high-accuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs. Index Terms—Analog-to-digital conversion, calibration, harmonic distortion, mixed analog–digital integrated circuits (ICs).

Phase-Noise Cancellation Design Tradeoffs in DeltaSigma Fractional-N PLLs

by Sudhakar Pamarti, Ian Galton - IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing , 2003
"... Abstract—A theoretical analysis of a recently proposed phasenoise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in 16 fractional- phasedlocked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop ..."
Abstract - Cited by 3 (2 self) - Add to MetaCart
Abstract—A theoretical analysis of a recently proposed phasenoise cancellation technique that relaxes the fundamental tradeoff between phase noise and bandwidth in 16 fractional- phasedlocked loops (PLLs) is presented. The limits imposed by circuit errors and PLL dynamics on the phase noise and loop bandwidth that can be achieved by PLLs incorporating the technique are quantified. Design guidelines are derived that enable customization of the technique in terms of PLL target specifications. Index Terms—Delta–sigma modulator, fractional- PLL, phased-locked loop (PLL), segmented digital-to-analog converter (DAC), synthesizer. I.

Quadrature Mismatch Shaping with a Complex, Tree Structured DAC

by Stijn Reekmans, Benoit Catteau, Pieter Rombouts, Ludo Weyten - in IEEE International Symposium on Circuits and Systems, ISCAS , 2006
"... Abstract — Quadrature bandpass (QBP) Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with near-perfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that sh ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract — Quadrature bandpass (QBP) Σ ∆ ADCs require a feedback path for both the I and the Q part of the complex feedback signal. A complex DAC could give this feedback with near-perfect I/Q balance. Still, the mismatch between the unit elements of the complex DAC introduces mismatch noise that should be shaped out of the signal band with dynamic elementmatching (DEM) techniques. To select the unit DAC elements of the complex multibit DAC, the well-known data directed swapper is generalized towards a complex structure and the necessary constraints for its correct functioning are derived. Additionally, a hardware efficient structure is presented: the reduced butterfly shuffler. Here, some of the QBP swapper cells are replaced by bandpass (BP) swapper cells. Also, great attention is paid to the interconnection pattern of the data directed swapper to prevent instability. I.

Quadrature Mismatch Shaping for Digital-to-Analog Converters

by Stijn Reekmans, Student Member, Jeroen De Maeyer, Student Member, Pieter Rombouts, Ludo Weyten
"... Abstract—Quadrature sigma–delta analog-to-digital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digital-toanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise i ..."
Abstract - Cited by 1 (0 self) - Add to MetaCart
Abstract—Quadrature sigma–delta analog-to-digital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digital-toanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to near-perfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the well-known butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient first-order QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance. Index Terms—Butterfly shuffler, mismatch shaping, quadrature bandpass (QBP), tree-structured, 61 analog-to-digital converters (ADCs). I.

A tight signal-band power bound on mismatch noise in a mismatch shaping digital-to-analog converter

by Jared Welz, Ian Galton - IEEE Trans. Inf. Theory , 2004
"... Abstract—Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its ..."
Abstract - Cited by 1 (1 self) - Add to MetaCart
Abstract—Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analog-to-digital, data converters, dc-free sequences, delta–sigma (16), digital-to-analog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.

LSB Dithering in MASH Delta–Sigma D/A Converters

by Sudhakar Pamarti, Ian Galton
"... Abstract—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can ..."
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Abstract—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither’s contribution to the power spectral density of the multistage digital 16 modulator’s output. A large class of popular multistage digital 16 modulators that satisfy the conditions are identified and tabulated for easy reference. Index Terms—Delta–sigma (16) modulation, dither techniques, MASH, quantization. I.
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