Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC’02 benchmark SOC that has been augmented with five analog cores. 1

Abstract: Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages very difficult. Testing packages with multi-gigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40 % of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an “intelligent ” manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented. Index Terms: SOP testing, analog system testing, built-in testing, digital system testing, automatic test equipment, design for testability, manufacturing testing, self-testing, built-off testing.

Gigahertz serialization and deserialization (SERDES) has become a dominant inter-chip and interboard data transmission technique. Signal integrity is the primary factor determining its bit error rate, typically less than 10-12, so the primary production test challenges are testing picosecond jitter and the signal eye opening. Off-chip jitter and rise/fall time measurements are limited by hardware complexity, access, bandwidth, and noise. Published on-chip measurement techniques are limited by delay line jitter. This paper presents a new jitter test technique that has been demonstrated on an FPGA to achieve less than 1 ps RMS self-jitter, and a new signal eye test that has unlimited bandwidth; neither test uses high speed circuitry. The all-digital technique uses the receiver itself to demodulate the signal jitter to a low-speed bit stream that is analyzed by a single-clock domain, synthesizable circuit. This is combined with logic BIST and 1149.6 boundary scan to completely test an IC.

Abstract—Many system-on-chips (SOCs) today contain both digital- and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC ’02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications. Index Terms—Full-chip testing, mixed-signal SOC testing, SOC testing, test access mechanism (TAM) optimization, test scheduling, wrapper design. I.