Results 1  10
of
10
A 13.5b 1.2V micropower extended counting A/D converter
 IEEE J. SolidState Circuits
, 2001
"... Abstract—This work presents a study of the extended counting technique for a 1.2V micropower voiceband A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. ..."
Abstract

Cited by 14 (1 self)
 Add to MetaCart
(Show Context)
Abstract—This work presents a study of the extended counting technique for a 1.2V micropower voiceband A/D converter. This extended counting technique is a blend of 61 modulation with its high resolution but relatively low speed and algorithmic conversion with its higher speed but lower accuracy. To achieve this, the converter successively operates first as a firstorder 61 modulator to convert the most significant bits, and then the same hardware is used as an algorithmic converter to convert the remaining least significant bits. An experimental prototype was designed in 0.8 m CMOS. With a 1.2V power supply, it consumes 150 W of power at a 16kHz Nyquist sampling frequency. The measured peak ƒ @x C „rhA was 80 dB and the dynamic range 82 dB. The converter core including the controller and all reconstruction logic occupies about I Q I mmP of chip area. This is considerably less than a complete 61 modulation A/D converter where the digital decimation filter would occupy a significant amount of chip area. Index Terms—Analogtodigital, extended counting, low power, low voltage. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
Abstract

Cited by 14 (0 self)
 Add to MetaCart
A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
An approach to tackle quantization noise folding in doublesampling 61 modulation A/D converters
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is ..."
Abstract

Cited by 6 (4 self)
 Add to MetaCart
(Show Context)
Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is twice the masterclock frequency. Unfortunately, path mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. Therefore, the performance is severely degraded. In this paper, we show that the problem is reduced but not eliminated by employing multibit quantization. Next, we present an indepth solution for the problem. The approach consists of modifying the quantization noise transfer function of the overall modulator to have one or several zeros at the Nyquist frequency. This way the effect of noise folding can nearly be eliminated. It is shown that this can be implemented by a simple modification of one of the integrators of the overall modulator circuit. Finally, several design examples of singlebit and multibit modulators are discussed. Index Terms—Analogtodigital conversion, doublesampling, spectral shaping.
A DoubleSampling ExtendedCounting ADC
 IEEE Journal of SolidState Circuits
, 2004
"... ..."
(Show Context)
unknown title
"... analogtodigital converters (ADCs) are becoming increasingly difficult to design in lowvoltage nanometerscale CMOS processes. We propose an ADC architecture based on a resetting modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A pro ..."
Abstract
 Add to MetaCart
(Show Context)
analogtodigital converters (ADCs) are becoming increasingly difficult to design in lowvoltage nanometerscale CMOS processes. We propose an ADC architecture based on a resetting modulator that achieves high resolution, despite poor component matching and poor analog transistor performance. A prototype design pipelines a secondorder resetting modulator and a 10 b cyclic ADC. The device achieves 14 b resolution and samples as a Nyquist converter at 23 MS/s. This calibrationfree ADC achieves no missing codes, 87 dB SFDR and 11.7 b ENOB. The ADC is fabricated in 0.18 m CMOS and occupies a core area of 0.5 mm. It consumes 48 mW from a 2 V supply. Index Terms—Analogdigital conversion, highresolution, integrator, modulator.
performance for sensor readout applications
, 2004
"... This work presents an ADC core for sensor readout applications. To achieve a high resolution combined with Nyquistrate A/D conversion, it employs the extended counting technique (IEEE Trans. Circuits Syst. I, 42(11) (1995) 904). By making the number of counting steps programmable, the circuit allow ..."
Abstract
 Add to MetaCart
(Show Context)
This work presents an ADC core for sensor readout applications. To achieve a high resolution combined with Nyquistrate A/D conversion, it employs the extended counting technique (IEEE Trans. Circuits Syst. I, 42(11) (1995) 904). By making the number of counting steps programmable, the circuit allows to trade conversion speed for accuracy. In its nominal (lowestaccuracy) mode a conversion requires 71 clock cycles and achieves 16bit performance in a conversion time of 50 ms: In the slowest, highestaccuracy mode it achieves 18bit performance in a conversion time of 365 ms: To achieve this in a CMOS process that only provides nonlinear capacitors, a nonlinearity correction is investigated. It is shown that this can be approximated by inverting the voltage to charge relationship of the capacitors at the output of the converter. This was implemented as a simple thirdorder correction, which can easily be done in software. If this correction is omitted, the DNL of the convertor is nearly unchanged but its INL is affected. The circuit’s power consumption is 5 mW. The silicon area including all control and reconstruction logic
An Alternative Method for Characterizing Capacitor Matching
"... Abstract – An alternative method for characterizing capacitor matching is presented. The basic idea of this method is to sense the mismatch among the capacitors by amplifying the error voltage using an iterative switchedcapacitor scheme. Through simulation, this method has shown attractive property ..."
Abstract
 Add to MetaCart
(Show Context)
Abstract – An alternative method for characterizing capacitor matching is presented. The basic idea of this method is to sense the mismatch among the capacitors by amplifying the error voltage using an iterative switchedcapacitor scheme. Through simulation, this method has shown attractive property for sensing capacitor mismatches down to 1 % and smaller.
, JangKyoo Shin
"... This paper proposes a single slope A/D converter (SSADC) that is possible to process the signal of the ultraviolet, visible and infrared rays with a single chip. And the proposed SSADC is a type of single channel ADC. In the conventional SSADC, it is possible to process the only one signal with a ki ..."
Abstract
 Add to MetaCart
This paper proposes a single slope A/D converter (SSADC) that is possible to process the signal of the ultraviolet, visible and infrared rays with a single chip. And the proposed SSADC is a type of single channel ADC. In the conventional SSADC, it is possible to process the only one signal with a kind of the sensor because the speed of the operating frequency and the slope of ramp signal generated by the ramp generator are fixed. In order to improve the disadvantages, a ramp generator which has variable slope in ramp function is designed and 3x1 MUX(multiplexer) is adopted so that we can change the speed of the operating frequency and the slope of ramp signal. Therefore, the multiple signal processing of the wanted sensors can be possible. The designed circuit is layout by the 0.35µm CMOS 2poly 4metal technology process and is checked through DRC and LVS tools.
LowPower Design Techniques for LowVoltage AnalogtoDigital Converters
, 2006
"... Abstract approved: ..."
(Show Context)