With the emergence of portable products as major players in the electronics market, controlling the power dissipation of integrated circuits is gaining increased importance. While progress is being made in improved battery technology to supply a larger amountofpower per unit weight of the battery,itmust also be coupled with an accompanying reduction in the power dissipation of IC's. Even for nonportable applications, as the system complexity increases, it is becoming more and more important to limit the power dissipation so as to avoid additional costs for cooling down electronic systems. In this context, it has become increasingly important to design CMOS digital circuits to ensure a lowpower dissipation. At the same time, however, it is also necessary to ensure that the speed of the circuit is not unduly sacri#ced. An additional consideration is the need for fast system turnaround times, which necessitates the use of semicustom design styles. In this work, we address a

The problem of designing individual macrocells for a library with power and speed considerations is addressed here. A new technique for optimization using posynomial [1] approximating functions is devised. In the design of each macrocell, optimality in design is critical and highly accurate techniques for measuring the performance are required during optimization. This paper presents methods for accurately estimating the worst-case contribution of the power and delay of a cell to a circuit. The program uses circuit-level simulation to calculate the power dissipation and delay of the cell with the highest accuracy.A rationale for using arbitrary degree posynomial modeling functions for area, delay and power modeling is presented. The problem is then formulated as a convex programming problem, and a rigorous optimization technique is used to arrive at the optimal macrocell.

As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not well-equipped to handle this scenario, since they do not model this statistical nature of the circuit parameters and performances, or if they do, the existing techniques tend to be over-simplified or intractably slow. We draw upon ideas for attacking parallel problems in other technical fields, such as computational finance, machine learning and hydrology, and synthesize them with innovative attacks for our problem domain of integrated circuits, to develop novel solutions to problems of efficient statistical analysis of circuits in the nanometer regime. In particular, this thesis makes three contributions: 1) SiLVR, a nonlinear response surface modeling (RSM) and performance-driven dimensionality reduction strategy, that uses the concepts of projection pursuit and latent variable regression to obtain an absolute improvement in modeling error of up to 34% over the best quadratic RSM method. SiLVR also captures the designer’s insight into the circuit behavior, by automatically extracting quantitative measures of relative