In the past decade, the limitations of models considering fixed (worst case) task execution times have been acknowledged for large application classes within soft real-time systems. A more realistic model considers the tasks having varying execution times with given probability distributions. Considering such a model with specified task execution time probability distribution functions, an important performance indicator of the system is the expected deadline miss ratio of the tasks and of the task graphs. This article presents an approach for obtaining this indicator in an analytic way. Our goal is to keep the analysis cost low, in terms of required analysis time and memory, while considering as general classes of target application models as possible. The following main assumptions have been made on the applications which are modelled as sets of task graphs: the tasks are periodic, the task execution times have given generalised probability distribution functions, the task execution deadlines are given and arbitrary, the scheduling policy can belong to practically any class of non-preemptive scheduling policies, and a designer supplied maximum number of concurrent instantiations of the same task graph is tolerated in the system. Experiments show the efficiency of the proposed technique for monoprocessor systems.

Current analytic solutions to the execution time prediction Y of binary parallel compositions of tasks with arbitrary execution time distributions X1 and X2 are either computationally complex or very inaccurate. In this paper we introduce an analytical approach based on the use of lambda distributions to approximate execution time distributions. This allows us to predict the first 4 statistical moments of Y in terms of the first 4 moments of X i at negligible solution complexity. The prediction method applies to a wide range of workload distributions as found in practice, while its accuracy is better or equal compared to comparable low-cost approaches.

Abstract. In the past, research on Multiprocessor Systems-on-Chip (MPSoC) has focused mainly on increasing the available processing power on a chip, while less effort was put into specific system-level performance analysis, or into behavior prediction. This paper introduces PAM-SoC, a light-weight performance predictor for MPSoC system-level performance. Being based on Pamela, a static performance predictor for parallel applications, PAM-SoC can compute its prediction in seconds for cases when cycle-accurate simulation takes tens of minutes. The paper includes a set of PAM-SoC validation experiments, as well as two sets of experiments to show how PAM-SoC can be used for either application tuning or MPSoC platform tuning in early system design phases. 1

Multimedia-dominated consumer electronics devices (such as cellular phone, digital camera, etc.) operate under soft real-time constraints. Overly pessimistic worst-case execution time analysis techniques borrowed from hard real-time systems domain are not particularly suitable in this context. Instead, the execution time distribution of a task provides a more valuable input to the system-level performance analysis frameworks. Both program inputs and underlying architecture contribute to the execution time variation of a task. But existing probabilistic execution time analysis approaches mostly ignore architectural modeling. In this paper, we take the first step towards remedying this situation through instruction cache modeling. We introduce the notion of probabilistic cache states to model the evolution of cache content during program execution over multiple inputs. In particular, we estimate the mean and variance of execution time of a program across inputs in the presence of instruction cache. The experimental evaluation confirms the scalability and accuracy of our probabilistic cache modeling approach. Categories and Subject Descriptors C.3 [Special-purpose and application-based systems]: Real-time and embedded systems.

Abstract. While most of the past research in the field of Multiprocessor Systems-on-Chip (MPSoC) has been dedicated to increasing the available processing power on a chip, less effort has been dedicated to analyze their system-level performance, or to predict their behavior. This paper introduces PAM-SoC, a performance predictor for MPSoCs system-level performance, based on adapting Pamela, a performance prediction tool for parallel applications, to the requirements of MPSoCs. We validate the proposed methodology with a set of five benchmark applications, whose performance is measured on the target MPSoC and compared to the behavior predicted by PAM-SoC on the same platform. The experiments show that PAM-SoC is able to correctly predict the behavior of various application types running on a MPSoC. 1

Current analytic solutions to the execution time distribu-tion of an N-ary parallel composition of tasks having in-dependent and identically distributed execution times are computationally complex, except for a limited number of distributions. In this paper we introduce an analytical so-lution based on approximating the execution time distribu-tions in terms of a limited number of statistical moments. This approach allows the parallel execution time to be ap-proximated with O ( 1) solution complexity for a wide range of execution time distributions, while the approximation ac-curacy outpegorms comparable techniques known to date. Experiments show that the error of the predicted mean value of the parallel execution time is even less than 4 % for par-allel loops comprising up to 10,000 tasks whose execution times are normally distributed. Measurements on real pro-grams (NAS-EP benchmark, PSRS sorteer; and WATOR sim-ulator) confirm these results provided the task execution dis-tributions are independent and unimodal. 1.

In this paper, we propose a formal analysis approach to estimate the expected (average) data cache access time of an application across all possible program inputs. Towards this goal, we introduce the notion of probabilistic access history that intuitively summarizes the history of data memory accesses along different program paths (to reach a particular program point) and their associated probabilities. An efficient static program analysis technique has been developed to compute the access history at all program points. We estimate the cache hit/miss probabilities and hence the expected access time of each data memory reference from the access history. Our experimental evaluation confirms the accuracy and viability of the probabilistic data cache modeling approach. Categories and Subject Descriptors