Modern embedded system execute a single application or a class of applications repeatedly. A new emerging methodology of designing embedded system utilizes configurable processors where the cache size, associativity, and line size can be chosen by the designer. In this paper, a method is given to rapidly find the L1 cache miss rate of an application. An energy model and an execution time model are developed to find the best cache configuration for the given embedded application. Using benchmarks from Mediabench, we find that our method is on average 45 times faster to explore the design space, compared to Dinero IV while still having 100 % accuracy. 1.

Today’s digital systems design requires extensive systemlevel simulation to ensure that the right architectural tradeoffs are made. In platform based designs a large number of platforms models must be executed for tuning the platform for the application. In order to run these simulations with adequate performance, design architects have increasingly employed abstract transaction-level models instead of RTL models to perform such analysis. Memory hierarchy is a major bottleneck for performance and energy consumption. Trying out every supported cache configuration to evaluate a given platform may become a very time consuming task. This paper proposes an approach for memory cache tuning, which is based on single-pass simulation. The proposed single-pass cache evaluation mechanism is 70 times faster than a simulation-based mechanism for the ADPCM application from Mediabench. 1