Abstract—Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increases in power consumption, and despite sustained system design efforts to address power demand, significant technological challenges remain that threaten to slow future bandwidth growth. In this paper we describe the power and associated heat management challenges in today’s routers. We advocate a broad approach to addressing this problem that includes making powerawareness a primary objective in the design and configuration of networks, and in the design and implementation of network protocols. We support our arguments by providing a case study of power demands of two standard router platforms that enables us to create a generic model for router power consumption. We apply this model in a set of target network configurations and use mixed integer optimization techniques to investigate power consumption, performance and robustness in static network design and in dynamic routing. Our results indicate the potential for significant power savings in operational networks by including power-awareness. I.

Abstract. We study the problem of non-preemptive scheduling to minimize energy consumption for devices that allow dynamic voltage scaling. Specifically, consider a device that can process jobs in a non-preemptive manner. The input consists of (i) the set R of available speeds of the device, (ii) a set J of jobs, and (iii) a precedence constraint Π among J. Each job j in J, defined by its arrival time aj, deadline dj, and amount of computation cj, is supposed to be processed by the device at a speed in R. Under the assumption that a higher speed means higher energy consumption, the power-saving scheduling problem is to compute a feasible schedule with speed assignment for the jobs in J such that the required energy consumption is minimized. This paper focuses on the setting of weakly dynamic voltage scaling, i.e., speed change is not allowed in the middle of processing a job. To demonstrate that this restriction on many portable power-aware devices introduces hardness to the power-saving scheduling problem, we prove that the problem is NP-hard even if aj = aj ′ and dj = dj ′ hold for all j, j ′ ∈ J and |R | = 2. If |R | < ∞, we also give fully polynomial-time approximation schemes for two cases of the general NP-hard problem: (a) all jobs share a common arrival time, and (b) Π = ∅ and for any j, j ′ ∈ J, aj ≤ aj ′ implies dj ≤ dj ′. To the best of our knowledge, there is no previously known approximation algorithm for any special case of the NP-hard problem. 1

Abstract. In this paper, we address the problem of high-level exploration of Network-on-Chip (NoC) architectures to early evaluate power/performance trade-offs. The main goal of this work is to propose a methodology supported by a design framework (namely, PIRATE) to generate and to simulate a configurable NoC–IP core for the power/performance exploration of the on-chip interconnection network. The NoC–IP core is composed of a set of parameterized modules, such as interconnection elements and switches, to form different on-chip micro-network topologies. The proposed framework has been applied to explore several network topologies by varying the workload and to analyze a case study designed for cryptographic hardware acceleration in high performance web server systems. 1

Abstract—Achieving effective run-time mapping on multiprocessor systems-on-chip (MPSoCs) is a challenging task, particularly since the arrival order of the target applications is not known apriori. This paper targets real-time applications which are dynamically mapped onto embedded MPSoCs, where communication happens via the Network-on-Chip (NoC) approach, and resources connected to the NoC have multiple voltage levels. We address precisely the energy- and performance-aware incremental mapping problem for NoCs with multiple voltage levels and propose an efficient technique (consisting of region selection and node allocation) to solve it. Moreover, the proposed technique allows for new applications to be added to the system with minimal interprocessor communication overhead. Experimental results show that the proposed technique is very fast, and as much as 50% communication energy savings can be achieved compared to using an arbitrary allocation scheme. Index Terms—Low-power design, multiprocessor interconnection, networks on chip (NoCs), optimization methods, real-time systems. I.

On-chip interconnection networks (OCNs) such as point-to-point networks and buses form the communication backbone in systems-on-a-chip, multicore processors, and tiled processors. OCNs can consume significant portions of a chip’s energy budget, so analyzing their energy consumption early in the design cycle becomes important for architectural design decisions. Although numerous studies have examined OCN implementation and performance, few have examined energy. This paper develops an analytical framework for energy estimation in OCNs and presents results based on both analytical models of communication patterns and real network traces from applications running on a tiled multicore processor. Our analytical framework supports arbitrary OCN topologies under arbitrary communication patterns while accounting for wire length, switch energy, and network contention. It is the first to incorporate the effects of communication locality and network contention, and use real traces extensively. This paper compares the energy of point-to-point networks against buses under varying degrees of communication locality. The results indicate that, for 16 or more processors, a one-dimensional and a two-dimensional point-to-point network provide 66 % and 82 % energy savings, respectively, over a bus assuming that processors communicate with equal likelihood. The energy savings increase for patterns which exhibit locality. For the two-dimensional point-to-point OCN of the Raw tiled microprocessor, contention contributes a maximum of just 23 % of the OCN energy, using estimated values for channel, switch control logic, and switch queue buffer energy of 34.5pJ, 17pJ, and 12pJ, respectively. Our results show that the energy-delay product per message decreases with increasing processor message injection rate. I.

We provide a power analysis for the communication in the Nostrum NoC concluding that power consumption is dominated by the links between switches while the switches and network interfaces contribute with a mere few percent to the power consumption. Further we analyze link level low power encoding techniques with the conclusion, that they spend several times more power than no encoding at all, if normalized for the same performance, which is done by adjusting supply voltage and frequency. Data protection schemes also have the potential to reduce power if voltage levels can be reduced and certain faults can be tolerated. We experiment with link level and endto -end data protection schemes. They only moderately increase power consumption and have indeed the potential to save power. However, this potential strongly depends on the application traffic patterns and fault models of future technology generations.

The On-Chip Communication Network (OCCN) project provides an efficient framework, developed within SourceForge, for the specification, modeling, simulation, and design exploration of network on-chip (NoC) based on an object-oriented C++ library built on top of SystemC. OCCN is shaped by our experience in developing communication architectures for different System-on-Chip (SoC). OCCN increases the productivity of developing communication driver models through the definition of a universal Application Programming Interface (API). This API provides a new design pattern that enables creation and reuse of executable transaction level models (TLMs) across a variety of SystemC-based environments and simulation platforms. It also addresses model portability, simulation platform independence, interoperability, and high-level performance modeling issues. 1.

The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus-invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay. 1.

Reducing power consumption is a main challenge when adopting a network as a global on-chip communication interconnect since the reduction in power dissipation should not at the expense of degrading the system performance. We investigate power in a wormhole-switched network with focus on the impact of flit-admission schemes, i.e., when and how the flits of packets are admitted into the network. We have proposed a novel flit-admission scheme that shows significant shrink of the switch complexity while maintaining equivalent network performance. This paper investigates its influence in network power involving both switches and links. We conduct experiments on a 2D mesh network. The results show that our flit-admission scheme achieves significant power and area reduction without performance penalty. To our knowledge, our work is the first study of power dissipation on flit admission schemes.

With decreasing feature size on silicon, the coupling capacitances of buses grow rapidly causing a significant impact on the power consumption of the whole chip. Thus, buses should be designed and optimized to dissipate less power without sacrificing performance. In this paper, we address this problem by simultaneously optimizing wire permutation, inversion and spacing (space between consecutive wires) using a combination of optimal as well as genetic algorithms. Unlike previous studies, our approach is applicable to not only address buses (behave more regularly), but also instruction buses of microprocessors. For the spacing problem, an algorithm is presented which determines the optimal solution instead of applying time consuming heuristic algorithms as presented in [10]. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. We simulate different combinations among permutation, spacing, and inversion. Integrated all optimization techniques together, our approach can save energy up to 68 % for the best case and 58 % on average while only increasing the total wire space by about 50 % (compared to a bus with minimal spacing between adjacent wires for a particular technology). 1.