In this paper, we present a general framework for evaluating the performance characteristics of block cipher structures composed of S-boxes and Maximum Distance Separable (MDS) mappings. In particular, we examine nested Substitution-Permutation Networks (SPNs) and Feistel networks with round functions composed of S-boxes and MDS mappings. Within each cipher structure, many cases are considered based on two types of S-boxes (i.e., 44 and 88) and parameterized MDS mappings. In our study of each case, the hardware complexity and performance are analyzed. Cipher security, in the form of resistance to differential, linear, and Square attacks, is used to determine the minimum number of rounds required for a particular parameterized structure.

Key elements of communication security include block ciphers and hash functions. Software implementations of these algorithms are relatively easy, but may not provide the speed necessary for some applications. For such applications, hardware implementations in ASIC or FPGA technology provide speed, but are difficult and time-consuming to develop. The SHERIF architecture described in this paper seeks to provide a flexible cryptographic hardware platform targeted for 0.18 micron CMOS technology, capable of greater speeds than software implementation while allowing for an ease of implementation not found in traditional hardware environments.