Programmable processors offer a high degree of flexibility and are therefore increasingly being used in embedded systems. We introduce the formalism nML which is especially suited to describe such processors in terms of their instruction set, an nML description is directly related to the standard description as found in the usual programmer's manuals. The nML formalism is based on a mixed structural and behavioural model facilitating exact yet concise descriptions. The philosophy of nML is already applied in two approaches to retargetable code generation and instruction set simulation. 1 Introduction In consumer electronics and telecommunications high product volumes are increasingly combined with short life-times and high system complexity. The pressure on development times together with the demand to react on late specification changes make mask or field programmability a desired feature. The thereby obtained flexibility not only helps to shorten the design cycle, but also allows fo...

Abstract Instruction selection is the primary task in automatic code generation. This paper proposes a practical system for performing optimal instruction selection based on tree pattern matching for expression trees. A significant feature of the system is its ability to perform code generation without requiring cost analysis at code generation time. The target machine instructions are specified as attributed production rules in a regular tree grammar augmented with cost information in Graham Glanville style. Instruction selection is modelled as a process of determining minimum cost derivation for a given expression tree. A matching automaton is used for instruction selection. Cost information is encoded into the states of this automaton so that cost analysis is not required at code generation time. The folding technique of table compression is extended to this automaton and two schemes of table compression based on cost information are proposed. Compilers Retargetable code generation Code-generator Code-generator-generator Tree-pattern matching Instruction selection Table compression

Due to the need for fast design cycles and low production cost, programmable targets like DSP processors are becoming increasingly popular. Design planning, detailed design as well as updating such designs requires mapping existing algorithms onto these targets. Instead of writing target-specific mappers, we propose using retargetable mappers. The technique reported in this paper is based on pattern matching. Binary code is generated as a result of this matching process. This paper describes the techniques of our mapper MSSV and identifies areas for improvements. As a result, it shows that efficient handling of alternative mappings is crucial for an acceptable performance. 1 Introduction For many years, research on high-level design tools was focused on high-level synthesis. High-level synthesis starts with a behavioral description and generates a structure with the same behavior. In most of the cases, the generated structure inplements just the given behavior. The limitation of that...

Domain-specific visual languages (DSVLs) are concise and useful tools that allow the rapid development of the behavior and/or structure of applications in well-defined domains. These languages are typically developed specifically for a domain, and have a strong cohesion to the domain concepts, which often appear as primitives in the language. The strong cohesion between DSVL language primitives and the domain is a benefit for development by domain experts, but can be a drawback when the domain evolves – even when that evolution appears insignificant. This paper presents a domain-specific visual language developed expressly for the evolution of domain-specific visual languages, and uses concepts from graph-rewriting to specify and carry out the transformation of the models built using the original DSVL. 1.

This paper presents new techniques in two different areas. Firstly, it proposes a solution to the problem of testing embedded processors. Towards this end, it discusses the automatic generation of executable test programs from a specification of test patterns for processor components. Secondly, the paper shows how constraint logic programming (CLP) improves the software production process for design automation tools. The advantages of CLP languages include: built-in symbolic variables and the built-in support for constraints over finite domains such as integers and Booleans. 1. INTRODUCTION During the recent years, there has been a significant shift in the way complex electronic systems are implemented: various types of embedded processors are being used in many designs. These types include: off-the-shelf DSPs (e.g. TMS320C25 [27]), application-specific instruction set processors (ASIPs, see e.g. [2]), application-specific signal processors (ASSPs) and in-house core processors. The ad...

retargetable compilers, table-driven compilers, machine description, processor description, instruction-level parallelism, EPIC processors, VLIW processors, EPIC compilers, VLIW compilers, code generation, scheduling, register allocation In the past, due to the restricted gate count available on an inexpensive chip, embedded DSPs have had limited parallelism, few registers and irregular, incomplete interconnectivity. More recently, with increasing levels of integration, embedded VLIW processors have started to appear. Such processors typically have higher levels of instruction-level parallelism, more registers, and a relatively regular interconnect between the registers and the functional units. The central challenges faced by a code generator for an EPIC (Explicitly Parallel Instruction Computing) or VLIW processor are quite different from those for the earlier DSPs and, consequently, so is the structure of a code generator that is designed to be easily retargetable. In this report, we explain the nature of the challenges faced by an EPIC or VLIW compiler and present a strategy for performing code generation in an incremental fashion that is best suited to generating high-quality code efficiently. We also describe the Operation Binding Lattice, a formal model for incrementally binding the opcodes and register assignments in an EPIC code generator. As we show, this reflects the phase structure of the EPIC code generator. It also defines the structure of the machine-description database, which is queried by the code generator for the information that it needs about the target processor. Lastly, we discuss general features of our implementation of these ideas and techniques in Elcor, our EPIC compiler research infrastructure.

I love you, and I’m proud of you too. Thanks for being here for me. Jon iii ACKNOWLEDGEMENTS I give many thanks to my advisor, Dr. Gabor Karsai for being the Best All-Around Advisor™. Gabor, without your excellent teaching skills and motivational abilities, I would not be in the position I am today. Vanderbilt is lucky to have you, as will be any other student under your tutelage. I also thank very heartily the other members of my committee. Dr. Janos Sztipanovits, for his political insight (and vision for my future career); Dr. Akos Ledeczi, for holding my feet to the fire when it comes to sticking up for the value of my research, and also social interactions within ISIS; Dr. Greg Nordstrom, for (as usual) providing valuable comments in the discussion of all things metamodeling related, not to mention being an all-around good guy to bounce ideas all-around with; and of course Dr. Doug

When developing software for embedded systems, the set of essential tools includes a compiler and an instruction set simulator. Since software and hardware are often designed in parallel, the tools must be easily adaptable to the changing target architecture. For the compiler, its back-end (the code generator) must be retargetable. Abstraction from the target machine is the key to an automated approach. Additionally, abstraction from tool-internal strategies permits the utilization of a unified machine description for all tools. In this chapter, the machine description formalism nML is presented along with the retargetable code generator Cbc and the instruction set simulation environment Sigh/Sim. 1 INTRODUCTION For the realization of retargetable software development tools such as a code generator and an instruction set simulator, several aspects of the potential target machines must be modeled in an abstract manner. These machine models are necessary to formalize the tool's methods...

Destination-driven code generation is a simple top-down technique that allows the code generated for a program phrase to depend upon its context in an abstract syntax tree. The context is encapsulated in a data destination and a control destination. The data destination specifies where the value computed by an expression is to be stored, while the control destination specifies where program execution is to resume after computation of the value. Together, the destinations allow a code generator to specify data and control flow dependencies between subcomputations. As a result, these subcomputations can be "wired" together in an efficient manner. We illustrate the technique by presenting a code generator for a subset of the programming language C. This technique has been used in the implementation of an incremental compiler for the Scheme programming language that generates code for one of several computer architectures.

Introduction Mobile and personal communication systems, and multi-media are among the most prominently growing sectors of the electronics industry today. As an illustration, Figure 1 gives an indication of the volume of some personal communication applications in the European market. New business and home applications are emerging, using advanced communication media such as satellite links, cellular radio, or high-speed optical networks. The success of these developments will however depend to a great extent on the ability to realise complex digital signal processing functionalities in cost-efficient VLSI chips. 1990 1992 1994 1996 40 30 20 10 0 Million users Cordless Cellular Paging Private mobile Figure 1. European market of personal communication systems (source : Elsevier Advanced Technology). The design of these chips is subject to stringent requirements in terms of processing performance and power dissipation. At the same