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Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
Online timing analysis for wearout detection
 In Proc. of the 2nd Workshop on Architectural Reliability (WAR
, 2006
"... CMOS feature size scaling has long been the source of dramatic performance gains. However, because voltage levels have not scaled in step, feature size scaling has come at the cost of increased operating temperatures and current densities. Further, since most common wearout mechanisms are highly dep ..."
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CMOS feature size scaling has long been the source of dramatic performance gains. However, because voltage levels have not scaled in step, feature size scaling has come at the cost of increased operating temperatures and current densities. Further, since most common wearout mechanisms are highly dependent upon both temperature and current density, reliability issues, and in particular microprocessor lifetime, have come into question. In this work, we explore the effects of wearout upon a fully synthesized, placed and routed implementation of an embedded microprocessor core and present a generic wearout detection unit. Since most common failure mechanisms may be characterized by a period of increased latency through ailing transistors and interconnects before breakdown, this wearout detection unit serves to predict imminent failure by conducting online timing analysis. In addition to measuring signal propagation latency, it also includes a unique twolevel sampling unit which is used to smooth out timing anomalies that may be caused by phenomenon such as temperature spikes, electrical noise, and clock jitter. 1.
BInterconnect delay minimization through interlayer via placement
 in 3D ICs,[ in Proc. ACM Great Lakes Symp. VLSI
, 2005
"... [pavlidis, friedman] @ ece.rochester.edu The dependence of the propagation delay of the interlayer 3D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location t ..."
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Cited by 8 (2 self)
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[pavlidis, friedman] @ ece.rochester.edu The dependence of the propagation delay of the interlayer 3D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location that minimizes the propagation delay of an interconnect line connecting two circuits on different planes is determined. The optimum vertical through via location and length or, equivalently, the number of physical planes traversed by the vertical through via, are determined for varying the placement of the connected circuits. Design expressions for the optimal via locations and lengths have been developed to support placement and routing algorithms for 3D ICs.
Interconnect Driver Design for Long Wires in FieldProgrammable Gate Arrays
, 2006
"... Designers of fieldprogrammable gate arrays (FPGAs) are always striving to improve the performance of their designs. As they migrate to newer process technologies in search of higher speeds, the challenge of interconnect delay grows larger. For an FPGA, this challenge is crucial since most FPGA imp ..."
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Designers of fieldprogrammable gate arrays (FPGAs) are always striving to improve the performance of their designs. As they migrate to newer process technologies in search of higher speeds, the challenge of interconnect delay grows larger. For an FPGA, this challenge is crucial since most FPGA implementations use many long wires. A common technique used to reduce interconnect delay is repeater insertion. Recent work has shown that FPGA interconnect delay can be improved by using unidirectional wires with a single driver at only one end of a wire. With this change, it is now possible to consider interconnect optimization techniques such as repeater insertion. In this work, a technique to construct switch driver circuit designs is developed. Using this method, it is possible to determine the driver sizing, spacing and the number of stages of the circuit design. A computeraided design model of the new circuit designs is developed to assess the impact they have on the delay performance of FPGAs. Results indicate that, by using the presented circuit design technique, the critical path can be reduced by 19 % for short wires, and up to 40 % for longer wires.
Statistical based link insertion for robust clock network design,” ICCAD
 Proc. of the ICCAD
, 2005
"... We present a statistical based nontree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show ..."
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We present a statistical based nontree clock distribution construction algorithm that starts with a tree and incrementally insert cross links, such that the skew variation of the final clock network is within a certain confidence interval under variations in wire width. Monte Carlo simulations show that the robustness of the final clock network can be significantly improved with a small increase in wire length. 1
Abstract Optimal Bus Sizing in Migration of Processor Design
"... The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor ..."
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Cited by 6 (4 self)
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The effect of wire delay on circuit timing typically increases when an existing layout is migrated to a new generation of process technology, because wire resistance and cross capacitances do not scale well. Hence, careful sizing and spacing of wires is an important task in migration of a processor to next generation technology. In this paper, timing optimization of signal buses is performed by resizing and spacing individual bus wires, while the area of the whole bus structure is regarded as a fixed constraint. Four different objective functions are defined and their usefulness is discussed in the context of the layout migration process. The paper presents solutions for the respective optimization problems and analyzes their properties. In an optimallytuned bus layout, after optimizing the most critical signal delay, all signal delays (or slacks) are equal. The optimal solution of the MinMax problem is always bounded by the solution of the corresponding sumofdelays problem. An iterative algorithm to find the optimallytuned bus layout is presented. Examples of solutions are shown, and design implications are derived and discussed. 1
Timing optimization of interconnect by simultaneous netordering, wire sizing and spacing
 Proc. ISCAS'06
, 2006
"... Abstract – This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are optimally shared for circuit timing optimization. Using an Elmore delay model including cross capacitances for a ..."
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Abstract – This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are optimally shared for circuit timing optimization. Using an Elmore delay model including cross capacitances for a bundle of wires, we show that an optimal wire ordering is uniquely determined, such that best timing can be obtained by proper allocation of wire widths and interwire spaces. The optimal order, called BMI (Balanced Monotonic Interleaved) depends only on the size of drivers for a wide range of cases. Heuristics are presented for simultaneous ordering, sizing and spacing of wires. Examples for 90nanometer technology are analyzed and discussed.
TimingAware PowerOptimal Ordering of Signals
"... A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that crosscapacitances between wires are optimally shared. The existence of a unique poweroptimal wire order ..."
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A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that crosscapacitances between wires are optimally shared. The existence of a unique poweroptimal wire order within a bundle is proven, and a method to construct this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence, it can be performed prior to spacing optimization. By using this order of wires, optimality of the combined solution is guaranteed (as compared with any other ordering and spacing of the wires). Timingaware power optimization is enabled by simultaneously considering timing criticality weights and activity factors for the signals. The proposed algorithm has been applied to various interconnect layouts, including wire bundles from highend microprocessor circuits in 65 nm technology. Interconnect power reduction of 17 % on average has been observed in such bundles.
On Optimal Ordering of Signals in Parallel Wire Bundles
"... Abstract — Optimal ordering and sizing of wires in a constrainedwidth interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average de ..."
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Abstract — Optimal ordering and sizing of wires in a constrainedwidth interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the MCF ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet nearoptimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65 nanometer process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10 % in wire delay, translated to about 5 % improvement in the clock cycle of a highperformance microprocessor implemented in that technology. Index Terms — routing, wire ordering, wire spacing C I.
Broadening the Scope of MultiObjective Optimizations in Physical Synthesis of Integrated Circuits
, 2010
"... would not have been possible without the immeasurable selfsacrifice of my perfect wife, Amy. She has worked day and night by my side for years to make our home and family prosperous. I love you very much. Our two beautiful sons George and Victor have brought me indescribable joy and gave me hope fo ..."
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would not have been possible without the immeasurable selfsacrifice of my perfect wife, Amy. She has worked day and night by my side for years to make our home and family prosperous. I love you very much. Our two beautiful sons George and Victor have brought me indescribable joy and gave me hope for the future when it seemed all was lost. I love you two in ways I never thought possible. I am eternally grateful to her for the faith she has placed in me. I will do everything I can to reward her investment. I am also deeply indebted to her parents Ren Fang Zhang and Yue Xia Gong who have come from their home in China to live with us and help raise our babies. Without them, I don’t know how it would be possible for me to balance graduate school, a fulltime job, and a new family. I will be sorry when they return home. My advisor, Professor Igor Markov, has also poured an incredible amount of work into training me to be capable of writing this dissertation. He has defended me when it was not convenient, supported me when it seemed hopeless, and never gave up on me until the task was complete. I am grateful for all of his efforts as well as all of the opportunities and second chances he has given me. I truly hope it has been as worth it for him as it has been