Abstract—The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage 16 modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35- m CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise C distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage. Index Terms—ADC, charge-pump circuits, delta–sigma, low voltage, sigma–delta, switched-capacitor circuits, switched opamp. I.

A low-voltage £¥ ¤ modulator, incorporating unitygain-reset opamps, is described. Due to the feedback structure, the opamps do not need to be switched off during operation, and hence can be clocked at a very high rate. A test chip, realized in a 0.35- ¦ m CMOS process and clocked at 10.24 MHz, provided a dynamic range (DR) of 80 dB and a signal-to-noise+distortion-ratio (SNDR) of 78 dB for a 20-kHz signal bandwidth, and DR = 74 dB and SNDR = 70 dB for a 50-kHz BW. 1.

Reduction of the power dissipation associated with high speed sampling and quantization is a major problem in many applications, including portable video devices such as camcorders, personal communication devices such as wireless LAN transceivers,

The power dissipation of an analog-to-digital converter (ADC) is a function of many variables, such as sampling rate (f S), resolution, architecture, process, voltage supply and technology. This chapter will attempt to establish the power dependence on sampling rate and resolution as its primary goal. To make this tenable, the scope of this task will be nar-rowed in the following two ways: 1. Architectures: Only those ADC’s suitable for use in high-speed signal processing applications, i.e., capable of attaining high Nyquist sampling rates, such as Flash, Two-step, Subranging, Folding, Interpolating and Pipelined architectures will be considered. 2. Process: Coverage will be restricted to high-integration capable IC processes such as bipolar, BiCMOS and CMOS processes which allow embedding of the ADC function in a monolithic signal processing chip. Even with a narrower scope, only a first-order analysis is attempted in light of the many variables that influence the power of an ADC. After developing power relationships for the above A/D architectures, the results of this analysis will be used to estimate the power 1 High-Speed ADC Architectures 2 variation in three high-speed system examples. 2.1 High-Speed ADC Architectures Before describing each architecture type, data gathered from published research of these types of ADC’s is presented for reference. In Fig.2-1, the resolution of the ADC’s is