Abstract—The problem of low-voltage operation of switched-capacitor circuits is discussed, and several solutions based on using unity-gain-reset of the opamps are proposed. Due to the feedback structure, the opamps do not need to be switched off during the reset phase of the operation, and hence can be clocked at a high rate. A low-voltage 16 modulator, incorporating pseudodifferential unity-gain-reset opamps, is described. A test chip, realized in a 0.35- m CMOS process and clocked at 10.24 MHz, provided a dynamic range of 80 dB and a signal-to-noise C distortion (SNDR) ratio of 78 dB for a 20-kHz signal bandwidth, and a dynamic range of 74 dB and SNDR of 70 dB for a 50-kHz bandwidth, with a 1-V supply voltage. Index Terms—ADC, charge-pump circuits, delta–sigma, low voltage, sigma–delta, switched-capacitor circuits, switched opamp. I.

Abstract—A four-stage fully differential power amplifier using a double nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and THD is-S3 dB for a 6-VP –P differential output signal at 10 kHz and a load of 50 Q. With 8-0 load and for a 10-kHz, 4-VP–P output signal, THD is-68 dB. The chip area is 0.625 mm ’ in a 1.5-~m single-poly, double-metal, n-well CMOS technology I.