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A doublesampling extendedcounting ADC
 IEEE J. SolidState Circuits
, 2004
"... Abstract—Extendedcounting analogtodigital conversion combines the accuracy of 61 modulation with the speed of algorithmic conversion. In this paper, a doublesampling technique is introduced for this type of converter. It is based on a variant of the fully floating bilinear integrator. This way, ..."
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Abstract—Extendedcounting analogtodigital conversion combines the accuracy of 61 modulation with the speed of algorithmic conversion. In this paper, a doublesampling technique is introduced for this type of converter. It is based on a variant of the fully floating bilinear integrator. This way, the clock frequency of the converter is almost halved. An experimental converter was designed in a 0.6 m CMOS technology for a bandwidth of 500 kHz at a 3.3V supply. In the switchedcapacitor implementation, the hardware is extensively reused. This way, the converter can be realized with only one operational amplifier. On the other hand, compared to alternative implementations, the amount of switches is increased. These are designed carefully in order not to degrade the performance. The converter converts a sample in 24 clock cycles and achieves a dynamic range of 87 dB. The peak signaltonoise ratio (SNR) and signaltonoiseplusdistortion ratio (SNDR) were measured to be 82 and 81 dB, respectively. The power consumption was 28mW analog and 20mW digital. The converter core occupies 0.7 mmP including digital logic. Index Terms—Analogtodigital conversion, double sampling, extended counting. I.
Design of doublesampling 61 modulation A/D converters with bilinear integrators
 IEEE Trans. Circuits Syst. I, Reg. Papers
, 2005
"... Abstract—Doublesampling techniques allow to double the sampling frequency of a switched capacitor 61 analogtodigital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator’s perfo ..."
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Abstract—Doublesampling techniques allow to double the sampling frequency of a switched capacitor 61 analogtodigital convertors without increasing the clock frequency. Unfortunately, path mismatch between the double sampling branches may cause noise folding, which could ruin the modulator’s performance. The fully floating doublesampling integrator is an interesting building block to be used in such a double sampling 61 modulator because its operation is tolerant to path mismatch. However, this circuit exhibits an undesired bilinear filter effect. This effectively increases the order of the modulator by one. Due to this, previously presented structures don’t have enough freedom to fully control the modulator pole positions. In this paper, we introduce modified topologies for doublesampling 61 modulators built with bilinear integrators. We show that these architectures provide full control of the modulator pole positions and hence can be used to implement any noise transfer function. Additionally, analytical expressions are obtained for the residual folded noise. Index Terms—Analogtodigital convertors, double sampling, 61 modulation. I.
Systematic design of doublesampling 61 A/D converters with a modified noise transfer function
 IEEE Trans. Circuits Syst. II, Exp. Briefs
, 2004
"... (ADCs) are sensitive to path mismatch which causes quantization noise to fold into the signal band. A recent solution for this problem consists of modifying the noise transfer function (NTF) of the modulator such that it has one or several zeros at the Nyquist frequency, next to those in the baseban ..."
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(ADCs) are sensitive to path mismatch which causes quantization noise to fold into the signal band. A recent solution for this problem consists of modifying the noise transfer function (NTF) of the modulator such that it has one or several zeros at the Nyquist frequency, next to those in the baseband. In this brief, we present a systematic design strategy for such ADCs. It consists of finding optimal pole positions for the modified NTF. This can be combined with optimizing the zeros as well. Next, we introduce several efficient structures that have enough degrees of freedom to realize the optimized pole positions. Index Terms—Analog–digital (A/D) conversion, double sampling, sigma–delta 61 modulation. I.
Mismatch Insensitive DoubleSampling Quadrature Bandpass 61 Modulation
"... Abstract—In a doublesampling quadrature bandpass sigma– delta modulator, path mismatch between the doublesampling branches and between the I/Q paths occurs. In this paper, an analytical study is presented which shows that this causes quantization noise and input signals to fold from the image band ..."
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Abstract—In a doublesampling quadrature bandpass sigma– delta modulator, path mismatch between the doublesampling branches and between the I/Q paths occurs. In this paper, an analytical study is presented which shows that this causes quantization noise and input signals to fold from the image band into the signal band and that this also results in a selfimage component. To reduce the folding from the image band, a novel resonator is presented. This resonator has a bilinear input circuit so that noise and signals exhibits firstorder shaping before folding in the band of interest. Next, three different modulator architectures based on the novel resonator are introduced. Finally, the remaining problem of selfimage is tackled with a simple, yet efficient offline calibration strategy. Various design examples are shown and simulated to illustrate and prove the effectiveness of the proposed architectures and methods. Index Terms—Analogtodigital (A/D) conversion, bilinear circuits, double sampling, sigma–delta (61 modulation. I.
On The Implementation of InputFeedforward Delta–Sigma Modulators
"... Abstract—This brief addresses some practical issues on the implementation of the inputfeedforward delta–sigma modulators. First, the timing constraint imposed by the inputfeedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog a ..."
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Abstract—This brief addresses some practical issues on the implementation of the inputfeedforward delta–sigma modulators. First, the timing constraint imposed by the inputfeedforward path is identified and a possible method to relax the constraint is proposed. Second, the drawbacks of the analog adder needed before the quantizer are explained and a method to eliminate the adder is proposed. Index Terms—Analogtodigital, delta–sigma(16), inputfeedforward, oversampling.