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Scheduling for reduced CPU energy
 USENIX SYMP. OPERATING
, 1994
"... The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing the energy used by displays and disks has been studied elsewhere; this paper considers a new method for reducing the energ ..."
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Cited by 470 (2 self)
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The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing the energy used by displays and disks has been studied elsewhere; this paper considers a new method for reducing the energy used by the cpu. We introduce a new metric for cpu energy performance, millionsofinstructionsperjoule (MIPJ). We examine a class of methods to reduce MIPJ that are characterized by dynamic control of system clock speed by the operating system scheduler. Reducing clock speed alone does not reduce MIPJ, since to do the same work the system must run longer. However, a number of methods are available for reducing energy with reduced clockspeed, such as reducing the voltage [Chandrakasan et al 1992][Horowitz 1993] or using reversible [Younis and Knight 1993] or adiabatic logic [Athas et al 1994]. What are the right scheduling algorithms for taking advantage of reduced clockspeed, especially in the presence of applications demanding ever more instructionspersecond? We consider several methods for varying the clock speed dynamically under control of the operating system, and examine the performance of these methods against workstation traces. The primary result is that by adjusting the clock speed at a fine grain, substantial CPU energy can be saved with a limited impact on performance.
Asymptotically Zero Energy SplitLevel Charge Recovery Logic
 In International Workshop on Low Power Design
, 1994
"... 1 As the clock and logic speeds increase, the energy requirements of CMOS circuits are rapidly becoming a major concern in the design of personal information systems and large computers. Earlier, we presented a new form of CMOS Charge Recovery Logic (CRL), with a power dissipation that falls with t ..."
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Cited by 51 (7 self)
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1 As the clock and logic speeds increase, the energy requirements of CMOS circuits are rapidly becoming a major concern in the design of personal information systems and large computers. Earlier, we presented a new form of CMOS Charge Recovery Logic (CRL), with a power dissipation that falls with the square of the operating frequency, as opposed to the linear drop of conventional CMOS circuits [1]. The technique relied on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its functional inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. In this paper, we present a new and greatly simplified form of CRL, we call it SplitLevel CRL (SCRL). Using splitlevel voltages, SCRL differs from our original CRL in that it needs only 2, instead of 16, times as many devices as conventional CMOS, requires only one wire for every si...
CRYSTALLINE COMPUTATION
 CHAPTER 18 OF FEYNMAN AND COMPUTATION (A. HEY, ED.)
, 1999
"... Discrete lattice systems have had a long and productive history in physics. Examples range from exact theoretical models studied in statistical mechanics to approximate numerical treatments of continuum models. There has, however, been relatively little attention paid to exact lattice models which o ..."
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Cited by 28 (7 self)
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Discrete lattice systems have had a long and productive history in physics. Examples range from exact theoretical models studied in statistical mechanics to approximate numerical treatments of continuum models. There has, however, been relatively little attention paid to exact lattice models which obey an invertible dynamics: from any state of the dynamical system you can infer the previous state. This kind of microscopic reversibility is an important property of all microscopic physical dynamics. Invertible lattice systems become even more physically realistic if we impose locality of interaction and exact conservation laws. In fact, some invertible and momentum conserving lattice dynamics—in which discrete particles hop between neighboring lattice sites at discrete times—accurately reproduce hydrodynamics in the macroscopic limit. These kinds of discrete systems not only provide an intriguing informationdynamics approach to modeling macroscopic physics, but they may also be supremely practical. Exactly the same properties that make these models physically realistic also make them efficiently realizable. Algorithms that incorporate constraints such as locality of interaction and invertibility can be run on microscopic physical hardware that shares these constraints. Such hardware can, in principle, achieve a higher density and rate of computation than any other kind of computer. Thus it is interesting to construct discrete lattice dynamics which are more physicslike both in order to capture more of the richness of physical dynamics in informational models, and in order to improve our ability to harness physics for computation. In this chapter, we discuss techniques for bringing discrete lattice dynamics closer to physics, and some of the interesting consequences of doing so.
Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design
 in Proceedings of the International Symposium on Low Power Electronics
, 1994
"... A technique called charge recovery or adiabatic switching has been proposed to trade speed for energy consumption in CMOS circuits. We compare the speed/power of charge recovery to standard CMOS logic operating at different supply voltages and demonstrate that the overhead of charge recovery limits ..."
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Cited by 14 (0 self)
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A technique called charge recovery or adiabatic switching has been proposed to trade speed for energy consumption in CMOS circuits. We compare the speed/power of charge recovery to standard CMOS logic operating at different supply voltages and demonstrate that the overhead of charge recovery limits the overall power savings. In almost all cases, voltage scaled CMOS dissipates less power for the same level of performance. Introduction Numerous researchers have shown that in theory computing engines do not need to dissipate energy [1] [2] [3]. Based on these principles, a technique to reduce the power dissipation of CMOS circuits has been proposed by [4] [5] [6] [7] and others. The technique, called charge recovery or adiabatic switching uses inductors and intermediate power supplies to provide a linear decrease in energy consumption with switching frequency. When clocked sufficiently slowly, charge recovery circuits approach zero energy consumption. While the promise of zero energy co...
True SinglePhase EnergyRecovering Logic for LowPower, HighSpeed VLSI
 In Proceedings of International Symposium on LowPower Electronics and Design
, 1998
"... In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multiphase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distrib ..."
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Cited by 11 (4 self)
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In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multiphase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for highspeed design due to clock skew management problems. In this paper, we present TSEL, the first energyrecovering logic family that operates with a singlephase clocking scheme. TSEL outperforms previous energyrecovering logic families in terms of energy efficiency and operating speed. In HSPICE simulations with a standard 0.5¯m technology from MOSIS, pipelined carrylookahead adders in TSEL function correctly for operating frequencies exceeding 280MHz. For operating frequencies above 80MHz, they dissipate considerably less energy per operation than alternative implementations of the same adder architecture in other energyrecovering l...
An EnergyEfficient CMOS Line Driver Using Adiabatic Switching
 Proc. 1994 IEEE Great Lakes Symposium on VLSI
, 1993
"... The energy recovery principle used in highefficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom linedriver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than ..."
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Cited by 9 (0 self)
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The energy recovery principle used in highefficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom linedriver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than conventional CMOS. The paper describes the adiabatic charging principle underlying this class of designs, which allows trading off switching time for increased energy efficiency. We emphasize the importance of including power supply and control logic overhead in evaluations of the net energy savings, and show how this overhead modifies the timeenergy tradeoff formula. The effect of nonideal devices is also investigated. The research described in this paper was supported by the Advanced Research Project Agency under contract number DABT6392C0052. November 2, 1993 1 1.0 Introduction Energy recovery in electronic circuits is a familiar principle in highefficiency power supply design[...
A True SinglePhase 8bit Adiabatic Multiplier
, 2001
"... This paper presents the design and evaluation of an 8bit adiabatic multiplier. Both the multiplier core and its builtin selftest logic have been designed using a true singlephase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal powerclock waveform that is g ..."
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Cited by 8 (3 self)
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This paper presents the design and evaluation of an 8bit adiabatic multiplier. Both the multiplier core and its builtin selftest logic have been designed using a true singlephase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal powerclock waveform that is generated onchip. In HSPICE simulations with postlayout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and selftest circuitry approaches 130pJ per operation at 200MHz. Our 11,854transistor chip has been fabricated in a 0.5 m standard CMOS process with an active area of 0.470mm . Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.
Nanocomputers and Reversible Logic
 Nanotechnol
, 1994
"... An overview of nanocomputers is given, including a discussion of reversible computing techniques and an explanation of why they are necessary. 1 Nanocomputers I usually begin this talk by trying to justify why we need nanocomputers in the first place. As Caxton Foster once said of associative memory ..."
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Cited by 5 (0 self)
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An overview of nanocomputers is given, including a discussion of reversible computing techniques and an explanation of why they are necessary. 1 Nanocomputers I usually begin this talk by trying to justify why we need nanocomputers in the first place. As Caxton Foster once said of associative memory, nanocomputers would seem to hold out the promise of sugar tomorrow to people drowing in honey today. However, I think that having an audience of people interested in molecular simulation makes that justification at least somewhat superfluous; present practice is straining quite firmly at the bounds of available computation. Instead I'll just point out a few of the qualititatively different uses nanocomputers will make economical. In the midsixties, IBM sold a small computer for what was then the average price of a house. Today, singlechip micros of roughly the same computational power cost less than $5 and are used as controllers in toasterovens. Similarly, we can imagine putting a n...
Driving FullyAdiabatic Logic Circuits Using Custom HighQ MEMS Resonators
"... To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flattopped) powerclock voltage waveform, which must be generated by a resonant element with a very high Q (quality factor). R ..."
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Cited by 4 (3 self)
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To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flattopped) powerclock voltage waveform, which must be generated by a resonant element with a very high Q (quality factor). Recently, MEMS resonators have attained very high frequencies and Q factors, and are becoming widely used in communications SoCs for RF signal filtering, amplification, etc. In the ADIAMEMS project at the University of Florida, we are designing custom MEMS resonators for driving fullyadiabatic pipelined logic based on the 2LAL (twolevel adiabatic logic) family previously developed at UF. The resonator design is being optimized to maximize its effective Q factor and area efficiency, at a frequency chosen to maximize the powerperformance advantage of the adiabatic logic. Our analyses indicate that the adiabatic approach will eventually lead to ordersofmagnitude improvements in powerperformance and even costperformance, compared to competing approaches, for all powerlimited applications. As competitive pressures drive down device costs, power dissipation will increasingly become the limiting factor on performance for most computing applications, and the advantages of the adiabatic approach will become ever greater.
Design, verification, and test of a true singlephase 8bit adiabatic multiplier
 In Proceedings of 19th Conference on Advanced Research in VLSI
, 2001
"... In this paper, we present the design and experimental evaluation of an 8bit adiabatic multiplier with builtin selftest (BIST) logic and an internal singlephase sinusoidal powerclock generatox Both the multiplier and the BIST have been designed in SCALD, a true singlephase adiabatic logic fami ..."
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Cited by 4 (2 self)
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In this paper, we present the design and experimental evaluation of an 8bit adiabatic multiplier with builtin selftest (BIST) logic and an internal singlephase sinusoidal powerclock generatox Both the multiplier and the BIST have been designed in SCALD, a true singlephase adiabatic logic family. In HSPICE simulations with postlayout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitry of 9lpJ per multiplication at IOOMHz. The chip has been fabricated in a 0.5pm standard CMOS process with an active area of 0.47mm2. Correct chip operation has been validated for operating frequencies up to I~OMHZ, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions. 1