The energy usage of computer systems is becoming more important, especially for battery operated systems. Displays, disks, and cpus, in that order, use the most energy. Reducing the energy used by displays and disks has been studied elsewhere; this paper considers a new method for reducing the energy used by the cpu. We introduce a new metric for cpu energy performance, millions-of-instructions-per-joule (MIPJ). We examine a class of methods to reduce MIPJ that are characterized by dynamic control of system clock speed by the operating system scheduler. Reducing clock speed alone does not reduce MIPJ, since to do the same work the system must run longer. However, a number of methods are available for reducing energy with reduced clock-speed, such as reducing the voltage [Chandrakasan et al 1992][Horowitz 1993] or using reversible [Younis and Knight 1993] or adiabatic logic [Athas et al 1994]. What are the right scheduling algorithms for taking advantage of reduced clock-speed, especially in the presence of applications demanding ever more instructions-per-second? We consider several methods for varying the clock speed dynamically under control of the operating system, and examine the performance of these methods against workstation traces. The primary result is that by adjusting the clock speed at a fine grain, substantial CPU energy can be saved with a limited impact on performance.

1 As the clock and logic speeds increase, the energy requirements of CMOS circuits are rapidly becoming a major concern in the design of personal information systems and large computers. Earlier, we presented a new form of CMOS Charge Recovery Logic (CRL), with a power dissipation that falls with the square of the operating frequency, as opposed to the linear drop of conventional CMOS circuits [1]. The technique relied on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its functional inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. In this paper, we present a new and greatly simplified form of CRL, we call it Split-Level CRL (SCRL). Using split-level voltages, SCRL differs from our original CRL in that it needs only 2, instead of 16, times as many devices as conventional CMOS, requires only one wire for every si...

In 1981, Richard Feynman gave a talk at a conference hosted by the MIT Information Mechanics Group. This talk was entitled "Simulating Physics with Computers," and is reproduced in this volume. In this talk Feynman asked whether it is possible that, at some extremely microscopic scale, nature may operate exactly like discrete computer-logic. In particular, he discussed whether crystalline arrays of logic called Cellular Automata (CA) might be able to simulate our known laws of physics in a direct fashion. This question had been the subject of long and heated debates between him and his good friend Edward Fredkin (the head of the MIT Group) who has long maintained that some sort of discrete classicalinformation model will eventually replace continuous different

In dynamic logic families that rely on energy recovery to achieve low energy dissipation, the flow of data through cascaded gates is controlled using multi-phase clocks. Consequently, these families require multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to clock skew management problems. In this paper, we present TSEL, the first energy-recovering logic family that operates with a single-phase clocking scheme. TSEL outperforms previous energy-recovering logic families in terms of energy efficiency and operating speed. In HSPICE simulations with a standard 0.5¯m technology from MOSIS, pipelined carry-lookahead adders in TSEL function correctly for operating frequencies exceeding 280MHz. For operating frequencies above 80MHz, they dissipate considerably less energy per operation than alternative implementations of the same adder architecture in other energyrecovering l...

The energy recovery principle used in high-efficiency power supplies can be applied to digital CMOS logic to reduce dynamic power dissipation. We describe experiments with a custom linedriver chip and resonant power supply that can switch eight 100pF loads at 1MHz over 6 times more efficiently than conventional CMOS. The paper describes the adiabatic charging principle underlying this class of designs, which allows trading off switching time for increased energy efficiency. We emphasize the importance of including power supply and control logic overhead in evaluations of the net energy savings, and show how this overhead modifies the time-energy trade-off formula. The effect of non-ideal devices is also investigated. The research described in this paper was supported by the Advanced Research Project Agency under contract number DABT63-92-C-0052. November 2, 1993 1 1.0 Introduction Energy recovery in electronic circuits is a familiar principle in high-efficiency power supply design[...

This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130pJ per operation at 200MHz. Our 11,854-transistor chip has been fabricated in a 0.5 m standard CMOS process with an active area of 0.470mm . Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations.

A technique called charge recovery or adiabatic switching has been proposed to trade speed for energy consumption in CMOS circuits. We compare the speed/power of charge recovery to standard CMOS logic operating at different supply voltages and demonstrate that the overhead of charge recovery limits the overall power savings. In almost all cases, voltage scaled CMOS dissipates less power for the same level of performance. Introduction Numerous researchers have shown that in theory computing engines do not need to dissipate energy [1] [2] [3]. Based on these principles, a technique to reduce the power dissipation of CMOS circuits has been proposed by [4] [5] [6] [7] and others. The technique, called charge recovery or adiabatic switching uses inductors and intermediate power supplies to provide a linear decrease in energy consumption with switching frequency. When clocked sufficiently slowly, charge recovery circuits approach zero energy consumption. While the promise of zero energy co...

We describe a CMOS signal driver that, while meeting the same speed constraints, dissipates considerably less power than the commonly thought to be unavoidable. We give a design procedure that, given the available charging time, yields a driver with minimum dissipation. We also describe an experimental circuit that confirms the predictions. The driver should be especially useful for off-chip drivers for high-speed microprocessors. The research described in this report was supported by the Advanced Research Project Agency under contract number DABT63-92-C-0052. fCV 2 Adiabatic charging without inductors 2 1 Introduction The main part of the power dissipation in most digital CMOS circuits is caused by repeatedly charging and discharging circuit node capacitances when nodes are switched from one logic level to the other. Until recently, this dissipation was commonly thought to be unavoidable. The only ways to decrease dissipation have been to decrease the switching frequency, the ci...

An overview of nanocomputers is given, including a discussion of reversible computing techniques and an explanation of why they are necessary. 1 Nanocomputers I usually begin this talk by trying to justify why we need nanocomputers in the first place. As Caxton Foster once said of associative memory, nanocomputers would seem to hold out the promise of sugar tomorrow to people drowing in honey today. However, I think that having an audience of people interested in molecular simulation makes that justification at least somewhat superfluous; present practice is straining quite firmly at the bounds of available computation. Instead I'll just point out a few of the qualititatively different uses nanocomputers will make economical. In the mid-sixties, IBM sold a small computer for what was then the average price of a house. Today, single-chip micros of roughly the same computational power cost less than $5 and are used as controllers in toaster-ovens. Similarly, we can imagine putting a n...

In this paper, we present the design and experimental evaluation of an 8-bit adiabatic multiplier with built-in self-test (BIST) logic and an internal single-phase sinusoidal power-clock generatox Both the multiplier and the BIST have been designed in SCAL-D, a true single-phase adiabatic logic family. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitry of 9lpJ per multiplication at IOOMHz. The chip has been fabricated in a 0.5pm standard CMOS process with an active area of 0.47mm2. Correct chip operation has been validated for operating frequencies up to I~OMHZ, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations for identical biasing conditions. 1