Abstract. The embedding of hardware description languages in functional programming languages has been actively explored for a number of decades, and a surprising number of such embedded languages have been developed and used. The first thing a developer of such a language realises, is the rich set of options and possible approaches. In this presentation, we discuss these issues, and examine their advantages and disadvantages in different settings, for languages developed with different objectives in mind. 1

To my parents, Henry and Karen Reeber, and my fiancée, Carrie Pankrast, for all their love, guidance, and support. Acknowledgments Most of all, I would like to thank my thesis advisor, Warren Hunt. Warren always has the amazing ability to give me what I need, before I even ask for it. Furthermore, Warren has been a source of constant encouragement and guidance, without which I never would have started this dissertation, let alone completed it. I would also like to thank the rest of my dissertation committee, Allen Emerson, Steve Keckler, J Moore, and Anna Slobodova, for all the time and energy they spent re-viewing my research and for their great feedback both on the dissertation itself and the earlier dissertation proposal. Anna in particular provided me with copious notes that have significantly improved the quality of this dissertation. Thanks also to Sandip Ray, Simha Sethumadhavan, and Jun Sawada for providing excellent feedback on portions of this dis-sertation. A number of professors at the University of Texas have influenced my work. My

Abstract: This paper focuses on the important, but tricky, problem of determining provably correct program properties automatically from program source. We describe a novel approach to constructing correct low-level programs. By using modern, full-spectrum dependent types, we are able to give an explicit and checkable link between the low-level program and its high-level meaning. Our approach closely links programming and theorem proving in that a type correct program is a constructive proof that the program meets its specification. It goes beyond typical model-checking approaches, that are commonly used to check formal properties of low-level programs, by building proofs over abstractions of properties. In this way, we avoid the state-space explosion problem that bedevils model-checking solutions. We are also able to consider properties over potentially infinite domains and determine properties for potentially infinite programs. We illustrate our approach by implementing a carry-ripple adder for binary numbers.

In efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a variant of the lambda calculus, called lλ (linear lambda), which may serve as a high-level substitute for netlists. In order to support higher-order functions, lλ uses a linear type system which enforces the linear use of variables of function type. The translation of lλ into structural descriptions of hardware circuits is sound and complete in the sense that it maps expressions only to realizable hardware circuits and that every realizable hardware circuit has a corresponding expression in lλ. To illustrate the use of lλ as a high-level substitute for netlists, we design a simple hardware description language that extends lλ with polymorphism, and use it to implement a Fast Fourier Transform circuit.

Abstract. Embedded languages have been used to support compositional descriptions for various domains. In this paper, we look at the domain of paper folding, or Origami-based geometry, in which sequences of paper folding are used to describe points and lines on the plane. Based on seven basic origami axioms, we design and develop an embedded domain specific language for the descriptions of such constructions in Haskell. We argue that the embedded language approach, that is composing a model using the basic constructors in the domain specific language, gives a compositional and concise way to describe Origami models. We look into analysis, manipulation and generation of origami models using this approach, including textual explanations of models, analysis of models to discover inherent preconditions (or constraints) in a description and basic animation of the folding of a model. Finally, we look into the tagging of blocks within a construction, enabling different evaluations at various levels of abstraction according to the user’s knowledge of Origami. 1

We develop a Haskell library for functional-logic programming, motivated by the implementation of Wired, a relational embedded domain-specific language for describing and analysing digital circuits at the VLSI-layout level. Compared to a previous library for logic programming by Claessen and Ljunglöf, we support residuation, easier creation of logical data types, and pattern matching. We discuss other applications of our library, including test-data generation, and various extensions, including lazy narrowing.

Abstract. General purpose functional languages such as Haskell, have been widely used as host languages for the embedding of domain specific languages. In particular, various hardware description languages have been successfully embedded in Haskell and other functional languages. More recently, meta-programming languages have also started being used for the embedding of such languages, where the meta-language features allow us to access the structure of data objects in a shallow-style embedding, while retaining the characteristics of a deep-embedding. In this paper, we discuss the application of meta-functional languages for the embedding of a hardware description language, based on reFLect, a functional meta-language which provides an alternative approach for embedding a hardware description language by means of built-in reflection features. Through the use of code quotation and pattern matching, we use reFLect to build a framework through which we can access the structure of our circuits by means of reflection. 1

Lava has been used successfully in structural circuit description and layout generation for FPGAs [2]. It has been demonstrated that Lava is suitable for describing so-called “clever ” or adaptive circuits – circuits whose structure adapts to properties of its context [4]. The rising problems associated with chip design in the deep sub-micron era call for new methods that are able to account for low-level effects already in higher-level descriptions. In particular, interconnect wires need to be modeled in order to get reliable estimates of non-functional properties, such as delay and power consumption. We are working on a system – Wired [1] – which aims to bring the ideas from Lava down to lower levels. What distinguishes Wired from other layout-aware languages is that wires are modelled explicitly. Also, we have settled on a relational model of information flow, giving some decoupling of information flow from the structural combinators, in the style of Ruby [3]. Wired supports a number of different circuit analyses. We can, for example, analyse for signal flow direction and delay. Our most advanced delay model

General purpose functional languages have been widely used as host languages for the embedding of domain specific languages, especially hardware description languages. The embedding approach provides various abstraction techniques, enabling the description of generators for whole families of circuits, in particular parameterised regular circuits. The twostage language setting that is achieved by means of embedding, provides a means to reason about the generated circuits as data objects within the host language. Nonetheless, these circuit objects lack information about their generators, or about the manner in which these where generated, which can be used for placement and analysis. In this paper, we use reFLect as a functional language with reflection features, to enable us not only to access the circuits, but also the circuit generators. Through the use of code quotation and pattern matching, we propose a framework through which we can access the structure of the circuit in terms of nested blocks that map the generation flow that was followed by the generator. 1

We have developed a formal verification approach that permits the mechanical verification of circuit generators and hardware optimization procedures, as well as existing hardware designs. Our approach is based on deeply embedding the DE2 HDL into the ACL2 logic [3]; we use the ACL2 theorem-proving system to verify the circuit generators. During circuit generation, a circuit generator may generate circuits based on variety of non-functional criteria. For example, a circuit generator may produce different structural circuit descriptions depending on wire lengths, circuit primitives, target technology, and circuit topology. In this paper, we show how we have applied the DE2 system to a simple circuit generator—the n-bit ripple-carry adder. We then show how we have applied the DE2 system to the verification of components of the TRIPS microprocessor design. 1