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Background calibration techniques for multistage pipelined ADCs with digital redundancy
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculati ..."
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Cited by 15 (6 self)
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Abstract—The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analogtodigital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A highaccuracy calibration is achieved by recalculating the digital output based on each stage’s equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A twochannel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16bit linearity can be achieved after calibration for an ADC with aHI7 capacitor mismatches and 60 dB opamp gain. Index Terms—Analogtodigital converter, capacitor mismatch, correlation, digital redundancy, finite opamp dc gain, multistage pipeline and algorithmic ADC, pseudorandom noise sequence, radixbased digital background calibration. I.
Digital Background Correction of Harmonic Distortion in Pipelined ADCs
 Circuits and System I: Regular Papers, IEEE Transactions on
, 2006
"... Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dom ..."
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Cited by 11 (3 self)
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Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in highresolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in highaccuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs. Index Terms—Analogtodigital conversion, calibration, harmonic distortion, mixed analog–digital integrated circuits (ICs).
A digitally enhanced 1.8V 15bit 40MSample/s CMOS pipelined ADC
 Univ of Calif Los Angeles. Downloaded on November 5, 2009 at 13:59 from IEEE Xplore. Restrictions apply. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL
, 2004
"... analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is ..."
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Cited by 8 (0 self)
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analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digitaltoanalog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signaltonoise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a lowlatency, segmented, dynamic elementmatching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the firststage residue amplifier to settle. The IC is realized in a 0.18 m mixedsignal CMOS process and has a die size of 4mm 5 mm. Index Terms—Analogtodigital conversion, calibration, mixed analog–digital integrated circuits (ICs).
A 1.8V 67mW 10bit 100MS/s pipelined ADC using timeshifted CDS technique
 IEEE Journal of SolidState Circuits
, 2004
"... Abstract—A timeshifted correlated double sampling (CDS) technique is proposed in the design of a 10bit 100MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple casco ..."
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Cited by 7 (2 self)
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Abstract—A timeshifted correlated double sampling (CDS) technique is proposed in the design of a 10bit 100MS/s pipelined ADC. This technique significantly reduces the finite opamp gain error without compromising the conversion speed, allowing the active opamp blocks to be replaced by simple cascoded CMOS inverters. Both highspeed and lowpower operation is achieved without compromising the accuracy requirement. An efficient commonmode voltage control is introduced for pseudodifferential architecture which can further reduce power consumption. Fabricated in a 0.18 m CMOS process, the prototype 10bit pipelined ADC occupies 2.5 mmP of active die area. With 1MHz input signal, it achieves 65dB SFDR and 54dB SNDR at 100 MS/s. For 99MHz input signal, the SFDR and SNDR are 63 and 51 dB, respectively. The total power consumption is 67 mW at 1.8V supply, of which analog portion consumes 45 mW without any opamp current scaling down the pipeline. Index Terms—Analogtodigital converter (ADC), correlated double sampling (CDS), data converter, high speed, low power, low voltage, pipeline. I.
A 12bit 20Msample/s pipelined analogtodigital converter with nested digital background calibration
 IEEE J. Solid State Circuits
, 2004
"... A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch a ..."
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Cited by 7 (0 self)
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A 12bit 20Msample/s pipelined analogtodigital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signaltonoiseanddistortion ratio (SNDR) of 70.8 dB, a peak spuriousfreedynamic range (SFDR) of 93.3 dB, a totalharmonic distortion (THD) of –92.9 dB, and a peak integral nonlinearity (INL) of 0.47 leastsignificant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm 2 in 0.35µm CMOS.
A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR
 IEEE J. SolidState Circuits
, 2005
"... Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling b ..."
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Cited by 5 (3 self)
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Abstract—An ultralowvoltage CMOS twostage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted lowvoltage circuit technique achieves highaccuracy highspeed clocking without the use of clock boosting or bootstrapping. A resistorbased input sampling branch demonstrates high linearity and inherent lowvoltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a twochannel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,
Background interstage gain calibration technique for pipelined ADCs
 IEEE Trans. Circuits and Syst. I
, 2005
"... A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The p ..."
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Cited by 5 (2 self)
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A background selfcalibration technique is proposed that can correct both linear and nonlinear errors in the interstage amplifiers of pipeline and algorithmic ADCs. Stage redundancy in a pipeline architecture is exploited to measure gain errors that are corrected using digital postprocessing. The proposed technique allows faster convergence and has less dependence on input signal statistics than a similar technique described in [1]. Simulation results are presented for a 12 bit pipelined ADC architecture, similar to that in [1], using nonideal interstage residue amplifiers. With calibration, the simulations show a SNDR performance of 72dB and a SFDR performance of 112dB, with calibration tracking time constants of approximately 8 x 10 5 sample periods, which is over 10 times faster than that reported in [1] at a similar performance level.
A 12Bit 200MHz CMOS ADC
"... Abstract—A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of th ..."
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Cited by 2 (0 self)
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Abstract—A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply. Index Terms—Adaptive systems, blind least mean square (LMS) calibration, lowgain op amp, nonlinearity correction, pipelined analogtodigital converter. I.
Digital Background Calibration for Memory Effects in Pipelined AnalogtoDigital Converters
"... capacitor circuits, dielectric materials. Abstract — Memory errors can occur in the stages of a pipelined ADC due to several effects. These include capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when op amps are shared betwee ..."
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Cited by 1 (0 self)
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capacitor circuits, dielectric materials. Abstract — Memory errors can occur in the stages of a pipelined ADC due to several effects. These include capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when op amps are shared between subsequent pipeline stages. This paper describes these sources of memory errors and the effect they have on overall ADC linearity. It is shown how these errors relate to and differ from interstage gain errors. Two new calibration algorithms are proposed that correct for memory errors by digital postprocessing of the ADC output. Both algorithms operate in the background and so do not require conversion to be interrupted in order to track changes due to temperature and supply variations. The two algorithms are compared in terms of their system costs and their dependence on input signal statistics. I.