this paper, we present techniques for energy efficient packet scheduling and fair queuing in wireless communication systems. Our techniques are based on an extensive slack management approach that dynamically adapts the output rate of the system in accordance with the input packet arrival rate. We use a recently proposed radio power management technique, dynamic modulation scaling (DMS), as a control knob to enable energy-latency trade-offs during wireless packet transmission. We first analyze a single input stream scenario, and describe a rate adaptation technique that results in significantly lower energy consumption (reductions of up to 10), while still bounding the resulting packet delays. By appropriately setting the various parameters of our algorithm, the system can be made to traverse the energy-latencyfidelity trade-off space. We extend our techniques to a multiple input stream scenario, and present WFQ, an energy efficient version of the weighted fair queuing (WFQ) algorithm for fair packet scheduling. Simulation results show that large energy savings can be obtained through the use of E WFQ, with only a small, bounded increase in worst case packet latency. Further, our results demonstrate that E WFQ does not adversely affect the throughput allocation (and hence, fairness) of WFQ

Media applications such as image processing, signal processing, and graphics require tens to hundreds of billions of arithmetic operations per second of sustained performance for real-time application rates, yet also have tight power constraints in many systems. For this reason, these applications often use special-purpose (fixed-function) processors, such as graphics processors in desktop systems. These processors provide several orders of magnitude higher performance efficiency (performance per unit area and performance per unit power) than conventional programmable processors.

Abstract—High fault tolerance for transient faults and lowpower consumption are key objectives in the design of critical embedded systems. Systems like smart cards, PDAs, wearable computers, pacemakers, defibrillators, and other electronic gadgets must not only be designed for fault tolerance but also for ultra-low-power consumption due to limited battery life. In this paper, a highly accurate method of estimating fault tolerance in terms of mean time to failure (MTTF) is presented. The estimation is based on circuit-level simulations (HSPICE) and uses a double exponential current-source fault model. Using counters, it is shown that the transient fault tolerance and power dissipation of low-power circuits are at odds and allow for a power fault-tolerance tradeoff. Architecture and circuit level fault tolerance and low-power techniques are used to demonstrate and quantify this tradeoff. Estimates show that incorporation of these techniques results either in a design with an MTTF of 36 years and power consumption of 102 W or a design with an MTTF of 12 years and power consumption of 20 W. Depending on the criticality of the system and the power budget, certain techniques might be preferred over others, resulting in either a more fault tolerant or a lower power design, at the sacrifice of the alternative objective. Index Terms—Fault sensitivity estimation, fault-tolerance techniques, low-power techniques, transient fault model. I.

This paper presents a resource allocation technique to design low power RTL datapaths. The basis of this technique is: a) to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles; b) to partition the circuit into n disjoint modules and assign each module to a distinct clock; and c) to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f=n to reduce power. However, the overall effective frequency of the circuit remains f , i.e. the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are reported. Keywords--- Low Power Design, Multiple Clock, NonOverlapping Clocks, Partitioning, Resource Allocation, Scheduling Information, Voltage-Power-Delay Tradeoffs. I. Introduction A ...

This paper presents an effective technique of low power design for RTL circuits and microarchitectures. The basis of this technique is: a) to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles; b) to partition the circuit into disjoint modules and assign each module to a distinct clock with frequency f=n. However, the overall effective frequency of the circuit remains f the single clock frequency. The results show that our multiple clocking scheme provides more effective power management (power savings up to 50%) at the RTL in comparison to conventional power management techniques based on gated clocks. 1. Introduction A major feature of currently proliferating portable applications is their requirement for low power consumption because they use battery voltage. Considering "power" rather than area or speed as the main optimization factor requires a second look at the entire VLSI design technologies, techniques, archi...

As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.

Abstract: A power consumption measurement framework for embedded processing systems is presented in this work. Given an assembly or machine level program as input to this setup, the energy consumption of the specific program in the specific processing systems may be estimated. The instruction level power models are derived based on the power supply current measurement technique. The instantaneous variations of the power supply current provide the appropriate information for the accurate estimation of the power consumption at different operating situations of the processor (core) and of the overall processing system as well (consumption of peripheral units). The proposed instantaneous current measuring approach, along with the execution of special test programs for analysis of inter-instruction effects provides a clear insight information of the power behavior of embedded processing systems.

Abstract. The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1

In this paper we present an e�cient technique to reduce the switching activity in a CMOS combina� tional logic network based onlocal logic transforma� tions. These transformations consist of adding redun� dant connections or gates so as to reduce the switch� ing activity. Simple and e�cient procedures � based on logic implication � for identifying the sources and tar� gets of the redundant connections are presented. Addi� tionally � procedures that permit the designer to trade� o � power and delay after the transformations are de� scribed. Results of experiments on the MCNC bench� mark circuits are given. The results indicate that signi�cant reduction of the switching activities of a CMOS combinational circuit can be achieved with a very low area overhead and low computational cost. 1

Our present ability to work with most multimedia data has been confined to a wired environment, requiring both the data source and the receiver to be physically connected to a power supply and a wired communication link. This article describes the design principles applicable to wireless signal processing systems, using a portable video-on-demand system as an example. The discussion will focus on both the algorithm and circuit design techniques developed for implementing a low-power video compression/decompression system at power levels that are two orders of magnitude below existing solutions. This low-power video compression system not only provides a compression efficiency similar to industry standards, but also maintains a high degree of error tolerance to guard against the transmission errors often encountered in wireless communication. Meng98 cusses low-power design principles; the section following that offers a brief overview of the compression algorithms developed for our portable video system and its error-tolerant capability for wireless communication under various channel error conditions. We then discuss the low-power architectural strategies employed in designing our decoder chipset. The amount of power savings achieved in each step will be quantified and substantiated by measured data. Finally, we offer our conclusions and outlook for the future.