Abstract—In this paper, we present a multiobjective hardware– software cosynthesis system, called SLOPES, for multirate low-power real-time distributed embedded systems consisting of dynamically reconfigurable field-programmable gate arrays (FPGAs), processors, and heterogeneous communication resources. This cosynthesis algorithm simultaneously optimizes system price and average power consumption. First, we present an evolutionary algorithm that automatically determines the quantities and types of system resources, assigns tasks to different potentially reconfigurable processing elements, and assigns communication events to communication resources. Second, we propose a dynamic priority multirate scheduling algorithm to determine the times at which all the tasks and communication events in the system occur. This two-dimensional scheduling algorithm determines task priorities based on real-time constraints and detailed frame-by-frame FPGA reconfiguration overhead information. Experimental results indicate that the proposed method reduces schedule length by an average of 34.3 % and reconfiguration energy by an average of 40.4%, compared to a method that does not consider the effect of partial reconfiguration during synthesis. SLOPES yields multiple system architectures that tradeoff system price and average power consumption under real-time constraints. Index Terms—Hardware–software co-design, low-power design, reconfigurable architectures, system-level synthesis. I.

The cosynthesis problem addressed in this paper involves three subproblems: selection of appropriate processing elements, mapping and scheduling of function blocks to the selected processing elements, and schedulability analysis. We have presented a cosynthesis framework in our earlier work X[1] X that defines an iteration loop of three steps that attack the subproblems separately. Despite many good features, our previous technique has a severe restriction that a task monopolizes the entire system once activated. But in general we may obtain higher performance if multiple tasks can be running concurrently on different processor cores. It is the main contribution of this paper that we extend the previous framework to be applicable for general multiprocessor systems with diverse operating policies. We demonstrate the performance improvement from the proposed work with a multi-media real-time application, DVR system, and randomly generated multi-task graphs. 1.

Abstract—This paper investigates an integrated approach for achieving fault tolerance and energy savings in real-time embedded systems. Fault tolerance is achieved via checkpointing, and energy is saved using dynamic voltage scaling (DVS). The authors present a feasibility analysis for checkpointing schemes for a constant processor speed as well as for variable processor speeds. DVS is then carried out on the basis of the feasibility analysis. The authors incorporate important practical issues such as faults during checkpointing, rollback recovery time, memory access time, and energy needed for checkpointing, as well as DVS and context switching overhead. Numerical results based on real-life checkpointing data and processor data sheets show that compared to fault-oblivious methods, the proposed approach significantly reduces power consumption and guarantees timely task completion in the presence of faults. Index Terms—Checkpointing, dynamic voltage scaling (DVS), fault tolerance, real-time scheduling. I.

Abstract — We present a hybrid energy management technique that exploits the variability of and correlations among the computational loads of tasks in a real-time application with soft timing constraints. In our technique, task load variability and correlations are captured in stochastic models that incorporate certain salient features and essential characteristics of the application. We use the stochastic models in formulating and solving the energy management problem for applications with soft timing constraints running on multiprocessor systems with dynamic voltage scaling (DVS). We present a novel optimization formulation for minimizing average energy consumption while providing a probabilistic guarantee for satisfying timing constraints.We compare our stochastic models and energy management scheme with other models and schemes that do not capture/exploit either the variability of or the correlations among the computational loads of tasks. I.

Abstract — Embedded real-time systems are becoming increasingly complex. To combat the rising design cost of those systems, co-synthesis tools that map tasks to systems containing both software and specialized hardware have been developed. As system transient fault rates increase due to technology scaling, embedded systems must be designed in fault tolerant ways to maintain system reliability. This paper presents and analyzes FD-HGAC, a tool using a genetic algorithm and heuristics to design real-time systems with partial fault detection. Results of numerous trials of the tool are shown to produce systems with average 22 % detection coverage that incurs no cost or performance penalty. I.

Abstract—In this paper, we present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In particular, we concentrate on distributed embedded systems that accommodate several different applications within a single device, i.e., multimode embedded systems. Based on the key observation that operational modes are executed with different probabilities, that is, the system spends uneven amounts of time in the different modes, we develop a new co-design technique that exploits this property to significantly reduce energy dissipation. Energy and cost savings are achieved through a suitable synthesis process that yields better hardware-resource-sharing opportunities. We conduct several experiments, including a realistic smart phone example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64 % are reported. Index Terms—Embedded systems, energy efficiency, multimode systems, power minimization, system-level cosynthesis. I.

Scan chains are widely used to improve the testability of integrated circuit (IC) designs and to facilitate fault diagnosis. For traditional 2D IC design, a number of design techniques have been proposed in the literature for scan-chain routing and scan-cell partitioning. However, these techniques are not effective for three-dimensional (3D) technologies, which have recently emerged as a promising means to continue technology scaling. In this article, we propose two techniques for designing scan chains in 3D ICs, with given constraints on the number of through-silicon-vias (TSVs). The first technique is based on a genetic algorithm (GA), and it addresses the ordering of cells in a single scan chain. The second optimization technique is based on integer linear programming (ILP); it addresses single-scan-chain ordering as well as the partitioning of scan flip-flops into multiple scan chains. We compare these two methods by conducting experiments on a set of ISCAS’89 benchmark circuits. The first conclusion obtained from the results is that 3D scan-chain optimization achieves significant wire-length reduction compared to 2D counterparts. The second conclusion is that the ILP-based technique provides lower bounds on the scan-chain interconnect length for 3D ICs, and it offers considerable reduction in wire-length compared to the GA-based heuristic method.