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Systematic design method for LC Bandpass SigmaDelta modulators with feedback FIRDACs
 International Symposium on Circuits and Systems ISCAS'06, 2006
"... Abstract — In this paper, a generalized technique for the design automation of fs LC bandpass Σ ∆ modulators using feedback 4 FIRDACs is proposed. The FIRDACs are used to increase the degrees of freedom in order to perform an exact equivalence with high order discretetime Σ ∆ modulators and also to ..."
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Abstract — In this paper, a generalized technique for the design automation of fs LC bandpass Σ ∆ modulators using feedback 4 FIRDACs is proposed. The FIRDACs are used to increase the degrees of freedom in order to perform an exact equivalence with high order discretetime Σ ∆ modulators and also to allow a more efficient circuit implementation of the LC filter. The design technique is based on Discrete TimeContinuous Time equivalence simplified by using the method of partial fractions expansion. The excess loop delay is taken into account without making more difficult the calculations since we define how to get the orders of the FIRDACs. Several examples of design are simulated with different values of excess loop delay. I.
Form and Content
, 1973
"... The HOL Light theorem prover can be difficult to get started with. While the manual is fairly detailed and comprehensive, the large amount of background information that has to be absorbed before the user can do anything interesting is intimidating. Here we give an alternative ‘quick start ’ guide, ..."
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The HOL Light theorem prover can be difficult to get started with. While the manual is fairly detailed and comprehensive, the large amount of background information that has to be absorbed before the user can do anything interesting is intimidating. Here we give an alternative ‘quick start ’ guide, aimed at teaching basic use of the system quickly by means of a graded set of examples. Some readers may find it easier to absorb; those who do not are referred after all to the
VariableStructure Compensation of DeltaSigma Modulators: Stability and Performance
 IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
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LOOP DELAY COMPENSATION IN BANDPASS CONTINUOUSTIME WITHOUT ADDITIONAL FEEDBACK COEFFICIENTS MODULATORS
"... Loopdelay is one of the major sources of instability and SignaltoNoiseRatio degradation in continuoustime bandpass modulators. In this paper, we use the modifiedztransform technique to calculate the value of the additional feedback coefficient required to compensate for the loopdelay. It is sh ..."
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Cited by 3 (3 self)
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Loopdelay is one of the major sources of instability and SignaltoNoiseRatio degradation in continuoustime bandpass modulators. In this paper, we use the modifiedztransform technique to calculate the value of the additional feedback coefficient required to compensate for the loopdelay. It is shown that, in certain conditions, this additional feedback coefficient can be removed and the loopdelay is compensated only by modifying the modulator coefficients. This is illustrated by several examples of loopdelay compensation in, and order bandpass modulators. 1.
TimeDomain Equivalent Design of ContinuousTime ΣΔ Modulators
 in Proc. IEEE International Conference on Electronics, Circuits, and Systems  ICECS
, 2010
"... A new design approach operating in the time domain for the design of ContinuousTime (CT) Σ ∆ modulators is presented. The method obtains CT modulators that are exactly equivalent to SampledTime (SD) counterpart without any constraint on the shape of feedback DACs responses. The procedure is suita ..."
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A new design approach operating in the time domain for the design of ContinuousTime (CT) Σ ∆ modulators is presented. The method obtains CT modulators that are exactly equivalent to SampledTime (SD) counterpart without any constraint on the shape of feedback DACs responses. The procedure is suitable and powerful for transistorlevel studies because design can be performed directly using circuit simulators. The effectiveness of the technique permits to account for the non idealities of integrators and DACs. Analytic study and behavioral simulation confirm the method. Index Terms — Continuous time systems, Sigma Delta modulation
A Wideband LowPower ContinuousTime DeltaSigma Modulator for Next Generation Wireless Applications
, 2007
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Design of RF/IF analog to digital converters for software radio communication receivers
, 2006
"... Software radio architecture can support multiple standards by performing analogtodigital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined ..."
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Software radio architecture can support multiple standards by performing analogtodigital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigmadelta (CT BP Σ∆) ADC based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only nonreturn to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining iii the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe
Sigma–Delta Modulators Operating at a Limit Cycle
"... Abstract—A new type of sigma–delta modulator that operates in a special mode named limitcycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a ..."
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Abstract—A new type of sigma–delta modulator that operates in a special mode named limitcycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital–analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A secondorder continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limitcycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs. Index Terms—Describing function (DF), limit cycles, sigma–delta modulation. I.
Multibit Continuous Time Σ∆ Modulators with a Reduced
 Number of Comparators,” WSEAS Trans. Circuits and Systems
, 2004
"... Abstract: A drawback of continuous time Σ∆modulators is their sensitivity to clock jitter. An appropriate way to counteract this is to use a multi bit feedback loop. This requires a high resolution multi bit quantizer. However, every extra bit in the quantizer doubles its complexity and power consu ..."
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Abstract: A drawback of continuous time Σ∆modulators is their sensitivity to clock jitter. An appropriate way to counteract this is to use a multi bit feedback loop. This requires a high resolution multi bit quantizer. However, every extra bit in the quantizer doubles its complexity and power consumption. In this paper, a new Σ∆modulator architecture is proposed. The implementation issues are discussed and the modulators ’ performance was compared with a conventional modulator through computer simulations. In the simulation examples the modulator had a quantizer with a quantization step corresponding to 6bit accuracy. Compared to the conventional modulator, the proposed architectures achieves the same performance while the required number of comparators in the high resolution quantizer can be reduced significantly.
A timeinterleaved continuoustime 16 modulator with 20 MHz signal bandwidth
 in Proc. ESSCIRC
, 2005
"... Abstract—This paper presents the first implementation results for a timeinterleaved continuoustime 16 modulator. The derivation of the timeinterleaved continuoustime 16 modulator from a discretetime 16 modulator is presented. With various simplifications, the resulting modulator has only a sing ..."
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Abstract—This paper presents the first implementation results for a timeinterleaved continuoustime 16 modulator. The derivation of the timeinterleaved continuoustime 16 modulator from a discretetime 16 modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A timeinterleaved by 2 continuoustime thirdorder lowpass 16 modulator is designed in a 0.18 m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signaltonoiseplusdistortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively. Index Terms—Analogtodigital conversion, continuoustime, deltasigma modulation, oversampling, timeinterleaving.