Abstract — In this paper, a generalized technique for the design automation of fs LC bandpass Σ ∆ modulators using feedback 4 FIRDACs is proposed. The FIRDACs are used to increase the degrees of freedom in order to perform an exact equivalence with high order discrete-time Σ ∆ modulators and also to allow a more efficient circuit implementation of the LC filter. The design technique is based on Discrete Time-Continuous Time equivalence simplified by using the method of partial fractions expansion. The excess loop delay is taken into account without making more difficult the calculations since we define how to get the orders of the FIRDACs. Several examples of design are simulated with different values of excess loop delay. I.

Loop-delay is one of the major sources of instability and Signal-to-Noise-Ratio degradation in continuous-time bandpass modulators. In this paper, we use the modified-ztransform technique to calculate the value of the additional feedback coefficient required to compensate for the loopdelay. It is shown that, in certain conditions, this additional feedback coefficient can be removed and the loop-delay is compensated only by modifying the modulator coefficients. This is illustrated by several examples of loop-delay compensation in, and order bandpass modulators. 1.

Abstract: A drawback of continuous time Σ∆-modulators is their sensitivity to clock jitter. An appropriate way to counteract this is to use a multi bit feedback loop. This requires a high resolution multi bit quantizer. However, every extra bit in the quantizer doubles its complexity and power consumption. In this paper, a new Σ∆-modulator architecture is proposed. The implementation issues are discussed and the modulators ’ performance was compared with a conventional modulator through computer simulations. In the simulation examples the modulator had a quantizer with a quantization step corresponding to 6bit accuracy. Compared to the conventional modulator, the proposed architectures achieves the same performance while the required number of comparators in the high resolution quantizer can be reduced significantly.

Software radio architecture can support multiple standards by performing analog-to-digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP Σ∆) ADC based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining iii the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe

Abstract—This paper presents the first implementation results for a time-interleaved continuous-time 16 modulator. The derivation of the time-interleaved continuous-time 16 modulator from a discrete-time 16 modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass 16 modulator is designed in a 0.18- m CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively. Index Terms—Analog-to-digital conversion, continuous-time, delta-sigma modulation, oversampling, time-interleaving.

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We develop a compensation method for continuous -time delta--sigma modulators valid for loop filters of arbitrary order. Our approach, based on variable-structure theory, accommodates multilevel quantization and dithering. Stability is rigorously proved under the assumption of infinite sampling rate and is accompanied by an analytic characterization of performance. A slight modification of the basic compensator provides a defence against parametric uncertainty through the use of variable-integrator damping.

Abstract—The maximum sampling rate of a continuous-time ΔΣ modulator is limited by quantizer delay. Most conventional delay compensation techniques address less than a clock cycle of delay. A technique previously proposed for compensating quantizer delays in excess of a clock cycle in bandpass modulators involves a parallel feedback path that bypasses the quantizer. We analyze this technique for low-pass modulators and show that sampling rates hitherto not possible can be achieved. Design tradeoffs are investigated, and simulation results showing the effectiveness of the technique are given. Index Terms—Analog-to-digital converter (ADC), compensation, continuous time, delta-sigma, excess loop delay (ELD), oversampling, quantizer, sample and hold (S/H). I.