On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential to increase power consumption. As feature sizes shrink, the dominant component of this power loss will be leakage. However, during a fixed period of time the activity in a cache is only centered on a small subset of the lines. This behavior can be exploited to cut the leakage power of large caches by putting the cold cache lines into a state preserving, low-power drowsy mode. Moving lines into and out of drowsy state incurs a slight performance loss. In this paper we investigate policies and circuit techniques for implementing drowsy caches. We show that with simple architectural techniques, about 80%-90 % of the cache lines can be maintained in a drowsy state without affecting performance by more than 1%. According to our projections, in a 0.07um CMOS process, drowsy caches will be able to reduce the total energy (static and dynamic) consumed in the caches by 50%-75%. We also argue that the use of drowsy caches can simplify the design and control of low-leakage caches, and avoid the need to completely turn off selected cache lines and lose their state.

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A micromechanical switch, dubbed the “resoswitch”, has been demonstrated that harnesses the resonance and nonlinear dynamical properties of its mechanical structure to greatly increase switching speed and cycle count (even under hot switching), and lower the needed actuation voltage, all by substantial factors over existing RF MEMS switches. The device comprises a wine-glass mode disk resonator driven hard via a 2.5V amplitude ac voltage at its 61-MHz resonance frequency so that it impacts electrodes along an orthogonal switch axis, thereby closing a switch connecting a 10V source to the switch electrode. The 61-MHz operating frequency corresponds to a switching period of 16ns with an effective rise time of <4ns, which is more than 200 times faster than the μs-range switching speeds of the fastest RF MEMS switches. Furthermore, since the voltage source is on during switching, the switch essentially hot switches with a demonstrated lifetime exceeding 16.5 trillion cycles without failure, but with some observed degradation.

Double-gated devices are expected to push transistor gate length scaling down to as low as 10 nm [1]. This technology may allow transistor scaling to continue for the next 15 years or more.

RF CMOS Class C Power Amplifiers for Wireless Communications by Ramakrishna Sekhar Narayanaswami Doctor of Philosophy in Engineering-Electrical Engineering and Computer Sciences University of California, Berkeley Abstract 2 order in order to generate an approximate solution to the design goal before a circuit analysis tool is required. Circuit techniques used to combat the technology limitations imposed by CMOS technologies include the use of differential circuits in the signal path, cascoded stages and a modified tuning method which allowed for the use of extremely large output devices but not requiring passive devices that were not feasible in a CMOS technology.

noise figure, scattering parameters, intermodulation distortion, second-order input