In this paper, we introduce an architecture description language for modeling, simulation, and evaluation of massively parallel processor architectures that are designed for special purpose applications from the domain of embedded systems. The architectural description of the processor system is supposed to be done according to two abstraction levels. Architectural parameters of processor elements are characterized on processor level and the interaction between processors (i.e., interconnect topology, positioning of the processors, etc.) is described on the array level. Key features, semantic, and technical innovations of the proposed architecture description language are demonstrated in this paper.

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Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems require more productive design approaches starting from high-level languages such as C. On the other hand, tight constraints of embedded systems require careful design exploration at system level (coarse grained exploration) and at the processing-element (PE) level (fine grained exploration). In this paper we presented GNR, a formal modeling approach, developed to improve productivity of designing systems and processing elements, the same way that traditional ADLs improved productivity for designing processors. The GNR is an order of magnitude shorter than state-of-the-art ADLs with RTL generation capabilities and yet can capture any structural details that affect the implementation quality. Using relatively short GNR description, we explored several designs for implementing an MP3 decoder and achieved 3.25 times speedup compared to MicroBlaze processor. We have also developed a web-based interface for our tools, so that users can upload and evaluate new architectures described in GNR. Our toolset and GNR is an intermediate step towards synthesis of TLM to RTL.

The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities. ii Acknowledgements I would like to thank my supervisors Jonathan Rose and Jason Anderson for their deep insights and advice on my thesis work and life in general.

Computer hardware is becoming increasingly complex. Nowadays, most personal computers are furnished with several cores sharing gigabytes of memory behind multi-level caches. Current hardware and

Abstract. Cross toolkits (assembler, linker, debugger, simulator, profiler) are widely used for software-hardware codesign; an early creation of cross toolkits is an important success factor for industrial embedded systems. At the hardware design stage systems are subject to significant design alterations including changes in the instruction set of target CPUs. This is a challenging issue for early cross toolkit development. In this paper, we present a new Architecture Description Language (ADL) called ISE language and an approach to early cross toolkit development to cope with hardware design changes. The paper introduces the MetaDSP framework that supports ISE-based construction of cross toolkits and gives brief overview of the MetaDSP applications to industrial projects that proves the industrial strength of the presented approach and tools. 1