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Scaling algorithms for the shortest paths problem
 In SODA ’93: Proceedings of the fourth annual ACMSIAM Symposium on Discrete algorithms
, 1993
"... Abstract. We describe a new method for designing scaling algorithms for the singlesource shortest paths problem and use this method to obtain an O (Vcfftn log N) algorithm for the problem. (Here n and m are the number of nodes and arcs in the input network and N is essentially the absolute value of ..."
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Cited by 56 (5 self)
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Abstract. We describe a new method for designing scaling algorithms for the singlesource shortest paths problem and use this method to obtain an O (Vcfftn log N) algorithm for the problem. (Here n and m are the number of nodes and arcs in the input network and N is essentially the absolute value of the most negative arc length; arc lengths are assumed to be integral.) This improves previous bounds for the problem. The method extends to related problems. Key words, shortest paths problem, graph theory, networks, scaling AMS subject classifications. 68Q20, 68Q25, 68R10, 05C70 1. Introduction. In
Monotonicity testing over general poset domains (Extended Abstract)
 STOC'02
, 2002
"... The field of property testing studies algorithms that distinguish, using a small number of queries, between inputs which satisfy a given property, and those that are ‘far’ from satisfying the property. Testing properties that are defined in terms of monotonicity has been extensively investigated, pr ..."
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Cited by 46 (23 self)
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The field of property testing studies algorithms that distinguish, using a small number of queries, between inputs which satisfy a given property, and those that are ‘far’ from satisfying the property. Testing properties that are defined in terms of monotonicity has been extensively investigated, primarily in the context of the monotonicity of a sequence of integers, or the monotonicity of a function over the £dimensional hypercube ¤¥¦§§ § ¦¨©�. These works resulted in monotonicity testers whose query complexity is at most polylogarithmic in the size of the domain. We show that in its most general setting, testing that Boolean functions are close to monotone is equivalent, with respect to the number of required queries, to several other testing problems in logic and graph theory. These problems include: testing that a Boolean assignment of variables is close to an assignment that satisfies a specific �CNF formula, testing that a set of vertices is close to one that is a vertex cover of a specific graph, and testing that a set of vertices is close to a clique. We then investigate the query complexity of monotonicity testing of both Boolean and integer functions over general partial orders. We give algorithms and lower bounds for the general problem, as well as for some interesting special cases. In proving a general lower bound, we construct graphs with combinatorial properties that may be of independent interest.
Scheduling with Timed Automata
, 2003
"... This document is based on the PhD thesis of the first author, defended at INPG Grenoble, November 2002 ..."
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Cited by 40 (4 self)
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This document is based on the PhD thesis of the first author, defended at INPG Grenoble, November 2002
Problems and results in combinatorial analysis
 COMBINATORICS (PROC. SYMP. PURE MATH
, 1971
"... This review of some solved and unsolved problems in combinatorial analysis will be highly subjective. i will only discuss problems which I either worked on or at least thought about. The disadvantages of such an approach are obvious, but the disadvantages are perhaps counterbalanced by the fact that ..."
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Cited by 38 (0 self)
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This review of some solved and unsolved problems in combinatorial analysis will be highly subjective. i will only discuss problems which I either worked on or at least thought about. The disadvantages of such an approach are obvious, but the disadvantages are perhaps counterbalanced by the fact that I certainly know more about these problems than about others (which perhaps are more important). i will mainly discuss finite combinatorial problems. I cannot claim completeness in any way but will try to refer to the literature in some cases; even so many things will be omitted. ISO will denote the cardinal number of S; c, cl, c2,... will denote absolute constants not necessarily the same at each occurrence. I. I will start with some problems dealing with subsets of a set. Let IS I =n. A well known theorem of Sperner [57] states that if A i a S, 15 i 5 m, is such that no A, contains any other, then max m=(aA). The theorem of Sperner has many applications in number theory; as far as I know these were first noticed by Behrend [2] and myself [8]. I asked 30 years ago several further extremal problems about subsets which also have number theoretic consequences. Let At a S, 15 i 5mi, assume that there are no three distinct A's so that Ai V A! = A,. I conjectured that
A simple algorithm for finding maximal network flows and an application to the Hitchcock problem
 CANADIAN JOURNAL OF MATHEMATICS
, 1957
"... ..."
Resource Spackling: A Framework for Integrating Register Allocation in Local and Global Schedulers
 In PACT `94: International Conference on Parallel Architectures and Compilation Techniques
, 1994
"... We present Resource Spackling, a framework for integrating register allocation and instruction scheduling that is based on a Measure and Reduce paradigm. The technique first measures the resource requirements of a program and then uses these measurements to distribute code for better resource alloca ..."
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Cited by 32 (7 self)
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We present Resource Spackling, a framework for integrating register allocation and instruction scheduling that is based on a Measure and Reduce paradigm. The technique first measures the resource requirements of a program and then uses these measurements to distribute code for better resource allocation. The technique is general in that it is applicable to both local and global scheduling and the allocation of different types of resources. A program's resource requirements for both register and functional unit resources are first measured using a unified representation. These measurements are used to find areas where resources are either underutilized or overutilized, called resource holes and excessive sets, respectively. Conditions are determined for increasing resource utilization in the resource holes. A local scheduler that moves sets of instructions into resource holes to reduce the excessive sets for all resources is presented. We develop a global scheduling algorithm that mo...
On Linear Layouts of Graphs
, 2004
"... In a total order of the vertices of a graph, two edges with no endpoint in common can be crossing, nested, or disjoint. A kstack (resp... ..."
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Cited by 30 (18 self)
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In a total order of the vertices of a graph, two edges with no endpoint in common can be crossing, nested, or disjoint. A kstack (resp...
Register binding and port assignment for multiplexer optimization
 PROCEEDINGS OF THE 2004 CONFERENCE ON ASIA SOUTH PACIFIC DESIGN AUTOMATION
, 2004
"... Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during highlevel synthesi ..."
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Cited by 27 (14 self)
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Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during highlevel synthesis are NPcomplete problems. In this paper, we first formulate a kcofamilybased register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44 % better overall than the leftedge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graphbased algorithm. For large designs, we are able to achieve significantly better results consistently. After technology mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption.