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Temes, “A noise-shaping accelerometer interface circuit for two-chip implementation (2000)

by T Kajita, U-K Moon, G C
Venue:in IEEE ISCAS 2000
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Temes, “A Two-Chip Interface for a MEMS Accelerometer

by Tetsuya Kajita, Student Member, Un-ku Moon, Senior Member, Gábor C. Temes, Life Fellow - IEEE Transactions on Instrumentation and Measurement , 2002
"... Abstract—A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is propos ..."
Abstract - Cited by 4 (0 self) - Add to MetaCart
Abstract—A proposed third-order noise-shaping accelerometer interface circuit enhances the signal-to-noise ratio, compared with previously presented interface circuits. The solution for the two-chip implementation is described and a novel cross-coupled correlated double sampling integrator is proposed. This scheme functions even with large parasitic capacitances between the sensor and the interface circuit. The op-amp noise is first-order shaped. Dithering circuit is also implemented on the chip, fabricated in an 1.6- m CMOS process. Index Terms—Accelerometer, correlated double sampling (CDS), delta–sigma modulator, dither, sensor interface. I.
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