: A novel modified method for obtaining approximate solutions to difficult optimization problems within the neural network paradigm is presented. We consider the graph partition and the travelling salesman problems. The key new ingredient is a reduction of solution space by one dimension by using graded neurons, thereby avoiding the destructive redundancy that has plagued these problems when using straightforward neural network techniques. This approach maps the problems onto Potts glass rather than spin glass theories. A systematic prescription is given for estimating the phase transition temperatures in advance, which facilitates the choice of optimal parameters. This analysis, which is performed for both serial and synchronous updating of the mean field theory equations, makes it possible to consistently avoid chaotic bahaviour. When exploring this new technique numerically we find the results very encouraging

VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

: This paper considers a solution to the school timetabling problem. The timetabling problem involves scheduling a number of tuples, each consisting of class of students, a teacher, a subject and a room, to a fixed number of time slots. A Monte Carlo scheme called simulated annealing is used as an optimisation technique. The paper introduces the timetabling problem, and then describes the simulated annealing method. Annealing is then applied to the timetabling problem. A prototype timetabling environment is described followed by some experimental results. A parallel algorithm which can be implemented on a multiprocessor is presented. This algorithm can provide a faster solution than the equivalent sequential algorithm. Some further experimental results are given. 1 INTRODUCTION This paper considers a solution to the school timetabling problem. The timetabling problem involves scheduling a number of tuples, each consisting of class of students, a teacher, a subject and a room, to a fixe...

Abstract-Floorplan design is an important stage in the VLSI design cycle. Designing a floorplan calls for arranging a given set of modules in the plane to minimize the weighted sum of area and wirelength mea-sures. This paper presents a method to solve the floorplan design prob-lem using distributed genetic algorithms. Distributed genetic algo-rithms, based on the paleontological theory of punctuated equilibria, offer a conceptual modification to the traditional genetic algorithms. Experimental results on several problem instances demonstrate the ef-ficacy of our method, and point out the advantages of using this method over other methods, such as simulated annealing. Our method has per-formed better than the simulated annealing approach, both in terms of the average cost of the solutions found and the best-found solution, in almost all the problem instances tried. I.

Abstract. In this study we have tackled the NP-hard problem of academic class scheduling (or timetabling) at the university level. We have investigated a variety of approaches based on simulated annealing, including mean-field annealing, simulated annealing with three different cooling schedules, and the use of a rule-based preprocessor to provide a good initial solution for annealing. The best results were obtained using simulated annealing with adaptive cooling and reheating as a function of cost, and a rule-based preprocessor. This approach enabled us to obtain valid schedules for the timetabling problem for a large university, using a complex cost function that includes student preferences. None of the other methods were able to provide a complete valid schedule. 1

I hereby declare that I am the sole author of this thesis. I authorize the University of Guelph to lend this thesis to other institutions or individuals for the purpose of scholarly research. I further authorize the University of Guelph to reproduce this thesis by photo-copying or by other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. ii The University of Guelph requires the signatures of all persons using or photo-copying this thesis. Please sign below, and give address and date. iii iv A VLSI chip can today contain millions of transistors and is expected to contain more than 100 million transistors in the next decade. This tremendous growth is made possible by the development of sophisticated design tools and software. To deal with the complexity

This paper presents an integrated framework for assembly design. The framework allows the designer to represent knowledge about the design process and constraints, as well as information about the artifact being designed, design history and rationale. Because the complexity of assembly design leads to extremely large design spaces, adequately supporting design space exploration is a key issue that must be addressed. This is achieved in part by allowing the designer to use both top-down and bottom-up approaches to assembly design. Exploration of the design space is further enabled by incorporating a simulated annealing-based optimization tool that allows the designer to rapidly complete partial designs, refine complete designs, and generate multiple design alternatives. INTRODUCTION In order to design and optimize a product, designers must be able to consider di#erent alternatives, perform analysis to guide their own design process and focus in on a "good", if not optimal, design. It i...

this paper, we address these shortcomings with a new datapath allocation method that consists of a new binding model construction scheme, and an optimization technique based on simulated annealing. It meets all three criteria: handling complex models of datapath units, using direct objective functions, and optimizing multiple objective functions simultaneously.

. Simulated annealing is an algorithm which generates near-optimal outcomes to combinatorial optimization problems. It is commonly thought to be slow. Cost-function approximation and parallel processing increase simulated annealing speed, but they can cause inaccuracies that degrade the outcome. Prior theoretical work has not adequately related cost-function inaccuracy to the run-time or quality of the outcome. We prove these results about annealing with inaccurate cost-functions: 1) Expected cost at equilibrium is exponentially affected by fl=T , where fl limits cost-function rangeerrors and T gives the temperature. 2) Expected cost at equilibrium is exponentially affected by (oe 2 \Gamma oe 2 )=2T 2 , when the errors have a Gaussian distribution. 3) Constraining fl to a constant factor of T guarantees convergence under a 1= log t temperature schedule. 4) A similar constraint guarantees convergence for a fractal space with a geometric temperature schedule. 5) Inaccuracies worse...

Recently, a very versatile algorithm for the design of finite word length filters has been proposed. The algorithm makes use of a simulated annealing algorithm which searches over discrete values of the filter coefficients. It has very fast development time and produces filters with good performances, its only drawback is a quite high execution time. In this paper, a detailed description of the particular annealing algorithm is presented together with three examples of filter design.