VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

Abstract-Floorplan design is an important stage in the VLSI design cycle. Designing a floorplan calls for arranging a given set of modules in the plane to minimize the weighted sum of area and wirelength mea-sures. This paper presents a method to solve the floorplan design prob-lem using distributed genetic algorithms. Distributed genetic algo-rithms, based on the paleontological theory of punctuated equilibria, offer a conceptual modification to the traditional genetic algorithms. Experimental results on several problem instances demonstrate the ef-ficacy of our method, and point out the advantages of using this method over other methods, such as simulated annealing. Our method has per-formed better than the simulated annealing approach, both in terms of the average cost of the solutions found and the best-found solution, in almost all the problem instances tried. I.

Most parallel algorithms for VLSI CAD proposed to date have one important drawback: they work efficiently only on machines that they were designed for. As a result, algorithms designed to date are dependent on the architecture for which they are developed and do not port easily to other parallel architectures. This paper describes a Portable object-oriented parallel environment for CAD algorithms (Prop- erCAD) under development at University of Illinois. The objectives of this research are two-fold. (1) To develop new parallel algorithms that are portable. We accomplish this by writing the algorithms using the ProperCAD environment: a library of functions that permits portability of parallel CAD algorithms across MIMD machines. Programs written using this environment run unchanged on all parallel machines for which this environment is available. (2) To design the parallel algorithms around a good sequential algorithm with a well-defined parallel-sequential interface. This will permit ...

Parallel algorithms developed for CAD problems today suffer from three important drawbacks. First, they are machine specific and tend to perform poorly on architectures other than the one for which they were designed. Second, they cannot use the latest advances in improved versions of the sequential algorithms for solving the problem. Third, the quality of results degrade significantly during parallel execution. In this paper we address these three problems for an important CAD application: standard cell placement. We have developed a new parallel placement algorithm that is portable across a range of MIMD parallel architectures. The algorithm is part of the ProperCAD project which allows the development and implementation of a parallel algorithm such that it can be executed on a wide variety of parallel machines without any change to the source. The parallel placement algorithm is based on an existing implementation of the sequential simulated annealing algorithm, TimberWolfSC 6.0 [1...

Abstract-Parallel algorithms with quality equivalent to the simu-lated annealing placement algorithm for standard cells [23] are pre-sented. The first, called heuristic spanning, creates parallelism by simultaneously investigating different areas of the plausible combina-torial search space. It is used to replace the high temperature portion of simulated annealing. The low temperature portion of Simulated An-nealing is sped up by a technique called section annealing, in which placement is geographically divided and the pieces are assigned to sep-arate processors. Each processor generates Simulated Annealing-style moves for the cells in its area, and communicates the moves to other processors as necessary. Heuristic spanning and section annealing are shown, experimentally, to converge to the same final cost function as regular simulated annealing. These approaches achieve significant speed-up over uniprocessor simulated annealing, giving high quality VLSI placement of standard cells in a short period of time. I.

Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been undertaken to parallelize this algorithm. Most previous parallel approaches to cell placement annealing have used a parallel moves approach. In this paper we investigate two new approaches that have been proposed for generalized parallel simulated annealing but have not been applied to the cell placement problem. Results are presented on the effectiveness of implementations of these algorithms when applied to the cell placement problem. We find that the first, multiple Markov chains, appears to be promising since it uses parallelism to obtain near linear speedups with no loss in quality. The second, speculative computation, while maintaining quality is not suitable since no speedups are achieved due to the specific nature of the cell placement problem. The two algorithms are compared with the parallel moves appr...

Abstract. Parallel implementationsof metaheuristicsappear quite naturally asan effective alternative to speed up the search for approximate solutions of combinatorial optimization problems. They not only allow solving larger problems or finding improved solutions with respect to their sequential counterparts, but they also lead to more robust algorithms. We review some trends in parallel computing and report recent results about linear speedups that can be obtained with parallel implementations using multiple independent processors. Parallel implementations of tabu search, GRASP, genetic algorithms, simulated annealing, and ant colonies are reviewed and discussed to illustrate the main strategies used in the parallelization of different metaheuristics and their hybrids. 1. Introduction. Although

Simulated annealing, a methodology for solving combinatorial optimization problems, is a very computationally expensive algorithm, and as such, numerous researchers have undertaken efforts to parallelize it. In this paper, we investigate three of these parallel simulated annealing strategies when applied to standard cell placement, specifically the TimberWolfSC placement tool. We have examined a parallel moves strategy, as well as two new approaches to parallel cell placement, multiple Markov chains and speculative computation. These algorithms have been implemented in ProperPLACE, our parallel cell placement application, as part of the ProperCAD II project. We have constructed ProperPLACE so that it is portable across a wide range of parallel architectures. Our parallel moves algorithm uses novel approaches to dynamic message sizing, message prioritization, and error control. We show that parallel moves and multiple Markov chains are effective approaches to parallel simulated annealin...

Despite the increasing availability of parallel platforms, their wide-spread use in the solution of large computing problems remains restricted to a fairly narrow set of applications. This is due in part to the difficulty of parallel application development which is itself largely the result of a lack of sophisticated environments for parallel application development. Further, though the number of parallel platforms is increasing, the convergence of parallel architectures and operating systems does not appear to be similarly increasing. Given that most development environments are targeted towards a particular architecture, it is difficult to amortize development costs over a wide base of installed machines. In this research, we address these problems through the application of two significant technologies, object-oriented design techniques and the actor model of concurrent computation. Our approach is manifested in the ProperCAD II library, a C ++ object library supporting actor concu...

this paper is the first one to evaluate parallel placement algorithms for the FPGA placement application. We have investigated a range of parallel simulated annealing algorithms for FPGA placement. The parallel moves approach does not seem very promising due to loss of speedup tight by synchronization requirements and degradation in quality of result because of restricted moves. The second approach of area based partitioning provides better speedups and quality of solution. The speedup obtained is mainly due to reduction in synchronization. In the same direction the Markov chains approach reduces the synchronization 13