Abstract—We present a two-stage congestion-driven placement flow. First, during each refinement stage of our multilevel global placement framework, we replace cells based on the wirelength weighted by congestion level to reduce the routing demands of congested regions. Second, after the global placement stage, we allocate appropriate amounts of white space into different regions of the chip according to a congestion map by shifting cut lines in a top-down fashion and apply a detailed placer to legalize the placement and further reduce the half-perimeter wirelength while preserving the distribution of white space. Experimental results show that our placement flow can achieve the best routability with the shortest routed wirelength among publicly available placement tools on IBM v2 benchmarks. Our placer obtains 100 % successful routings on 16 IBM v2 benchmarks with shorter routed wirelengths by 3.1 % to 24.5 % compared to other placement tools. Moreover, our white space allocation approach can significantly improve the routability of placements generated by other placement tools. Index Terms—Circuit placement, design automation, routability, white space allocation. I.

A new paradigm is introduced for floorplanning any combination of fixed-shape and variable-shape blocks under tight fixed-outline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsize-driven, top-down hierarchy. By scalably incorporating legalization into the hierarchical flow, post-hoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of state-of-the-art floorplanners in orders of magnitude less run time. Experiments on standard GSRC industry benchmarks compare an implementation, called PATOMA, to the Traffic floorplanner and to both the default and high-effort modes of the Parquet-2 floorplanner. With all blocks hard, PATOMA’s average wirelength is 38 % shorter than Traffic’s in the same run time. With all blocks soft, PATOMA on average produces wirelengths 16 % shorter than Parquet-2’s default mode and runs 37 ¢ faster. Compared to the high-effort mode of Parquet-2, PATOMA’s average wirelength is 8 % shorter, and it runs 824 ¢ faster, on average. I.

Inspired by recent success of analytical placers that use a logarithmsum-exponential (LSE) to smooth half-perimeter wirelength (HPWL), we consider in this paper two alternative smoothing methods for HPWL by recursive extension of two-variable max functions. A limited memory Quasi-Newton solver is applied to solve the objective function combining both the smoothing function of HPWL and the penalty function that arises from cell density constraints. Experimental results show that our flow using these two smoothing functions and the solver produces placements with comparable HPWL compared to LSE smoothing-based methods. Our placement flow also produces placements with comparable routability and routed wirelength but with shorter runtime. 1.

At every stage in physical design, engineers are faced with many different objectives and tools to develop, optimize, and evaluate their design. Each choice of a tool or an objective to optimize can potentially lead to a completely different final physically designed circuit. Furthermore, some of the objectives optimized by the tools are not necessarily the best or right objectives, but rather compromised objectives; for example, placers optimize the half-perimeter wirelength rather than the routed wirelength. The contributions of this paper are twofold. First, we define and use a metric to measure the consistency of optimizing wirelength during the different stages of physical design. Our main technique is based on tracing the relative lengths of two nets- or more accurately pairs of nets- as they progress through the physical design flow. Second, we propose a simple method to quantify the similarity between the results of different tools. Our empirical results point out to the physical design stages where vulnerability can occur from optimizing compromised objectives.

We present a rigorous framework that defines a class of net weighting schemes in which unconstrained minimization is successively performed on a weighted objective. We show that, provided certain goals are met in the unconstrained minimization, these net weighting schemes are guaranteed to converge to the optimal solution of the original timingconstrained placement problem. These are the first results that provide conditions under which a net weighting scheme will converge to a timing optimal placement. We then identify several weighting schemes that satisfy the given convergence properties and implement them, with promising results: a modification of the weighting scheme given in [11]results in consistently improved delay over the original, 4 % on average, without increase in computation time. 1.

Approaches for solving the timing-driven placement problem have traditionally been either net-based or path-based; see, e.g., [7] for an overview. Net weighting methods, which fall in the latter category, have been a popular tool in analytical placers [16, 8, 9] for handling timing-driven placement. They enjoy a number of advantages, including very low computational complexity, high flexibility, and ease

In this paper we introduce the concept of zero-change netlist transformations to (1) quantify the suboptimality of existing placers on artificially constructed instances, and (2) “partially ” quantify the suboptimality of placers on synthesized netlists from arbitrary netlists by giving lower bounds to the suboptimality gap. Given a netlist and its placement from a placer, we formally define a class of netlist transformations that synthesize a different netlist from the given netlist but yet the new netlist has the same Half-Perimeter Wire Length (HPWL) on the given placement. Furthermore, and more importantly, the optimal HPWL value of the new netlist is no less than that of the original netlist. By applying our transformations and re-executing the placer, we can interpret any deviation in HPWL as a lower bound to the gap from the optimal HPWL value of the new synthesized netlist. Our transformations allow us to (1) increase the cardinality of hyperedges, (2) reduce the number of hyperedges, and (3) increase the number of two-pin edges, while maintaining the placement HPWL constant. We also develop methods that apply zero-change netlist transformations to synthesize netlists having typical netlist statistics. Furthermore, we extend our approach to estimate suboptimality of other metrics such as rectilinear minimum-spanning tree (RMST) and minimum-Steiner tree. Using these transformations, the suboptimality of some of the existing academic placers (FengShui [35], Capo [4], mPL [10], Dragon

Abstract not found

(NRE) costs associated with the development of Integrated Circuits (ICs) is becoming extremely high. One of the main reasons is the high cost of preparing and processing IC fabrication masks. The design effort and cost can be reduced by employing Structured Application-Specific ICs (Structured ASICs). Structured ASICs are partially fabricated ICs that require only a subset of design-specific custom masks for their completion. In this dissertation, we investigate the impact of design-specific masks on the area, delay, power, and die-cost of Structured ASICs. We divide Structured ASICs into two categories depending on the types of masks (metal and/or via masks) needed for customization: Metal-Programmable Structured ASICs (MPSAs) that require custom metal and via masks; and Via-Programmable Structured ASICs (VPSAs) that only require custom via masks. We define the metal layers used for routing that can be configured by one or more via, or metal-and-via masks as configurable layers. We then investigate the area, delay, power, and cost trends for MPSAs and VPSAs as a function of configurable layers.

Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a design. Traditionally, it is applied after the logic synthesis stage and before the routing stage. Since the advent of deep submicron process technology around the mid-1990s, interconnect delay, which is largely determined by placement, has become the dominating component of circuit delay. As a result, placement information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the logic synthesis stage to perform physical synthesis and into the architecture design stage to perform physical-aware architecture design. This chapter begins with an introduction to the placement stage. Next, various placement problem formulations are discussed. Then, partitioning-based approach, simulated annealing approach, and analytical approach for global placement are presented. After that, legalization and detail placement algorithms are