informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

This paper studies power modeling for Field Programmable

A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis. This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN optimization problem is much more difficult; the few existing methods cannot handle large-scale problems.

Abstract — This paper revisits and extends a general linear programming (LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgatebiasing to minimize total leakage power under timing constraints. We minimize positive timing slack for each cell according to its leakage vs. delay sensitivity, so that unnecessary leakage power consumption is saved without degrading circuit performance. A key difference between our work and previous works is that we pre-process timing libraries to estimate the linear relation – in every slew-load condition – between the gate delay and gate length by linear fitting; we then optimize total leakage power by estimating the optimal gate length for each gate using fast linear programming. With a 65GP industry testbed, and directly comparing with commercial tools, we show the QOR and runtime advantages of our method for the multi-Lgate and Lgate-biasing knobs. We also show a promising application to circuit timing legalization, a problem which frequently arises when implementation and signoff timers differ. Overall, our results show strong viability of LP based estimation and optimization: compared with the commercial tools, we: (1) shift the achievable delay-leakage tradeoff curve in a positive way, and (2) more accurately maintain prescribed timing constraints.

Abstract — In this paper, a scheme for power reduction based on Cluster Voltage Scaling (CVS) for gate-level design of the VLSI circuits is presented. To increase the power reduction efficiency of the previous CVS techniques, a new low power level-shifter is utilized in the circuit. In addition, the concept of transistor ordering has been used to further reduce the power consumption. This technique shows an average improvement of 7 % compared to the previous CVS circuits. The impact of CVS and its modified version on the reduction of short-circuit and leakage power are also discussed. I.

Abstract. Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft error rates caused by single event upsets (SEU) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at the sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a non-linear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit, we prove that it is sufficient to consider a linear number of constraints. As an important preprocessing step we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100 % to 200 % while, on average, the power saving is simultaneously decreased by less than 7 % to 12 % respectively, compared to the optimal power saving with no error rate constraints. 1

To my adorable mom and lovely wife whom unconditional love and support made this work possible. ii ACKNOWLEDGEMENTS I am most grateful to my advisor, Professor Massoud Pedram, for inviting me to join his research group and providing invaluable support and guidance throughout my Ph.D. studies at USC. He has been a continuous source of motivation for me and I want to sincerely thank him for all I have achieved. His multi-disciplinary approach and global vision of research problems have been instrumental in defining my professional career. I would also like to thank my other committee members, Professor Jeff Draper and Professor Aiichiro Nakano for their insightful suggestions and for their valuable time. I am sincerely grateful to Dr. Farzan Fallah for his guidance in some parts of my Ph.D. research and his help and support during my internship at Fujitsu Laboratories of America. I would also like to extend my appreciation to Dr. Amir H. Ajami for his