Reversible logic is motivated by low-power design, quantum circuits and nanotechnology. We develop a compact representation of small reversible circuits to generate and store optimal circuits for all 40,320 three-input reversible functions, and millions of four-input circuits. This allows implementing a function optimally in constant time for use in peephole optimization of larger circuits produced by existing techniques, and guarantees that every three-bit subcircuit is optimal. To generate subcircuits, we use a graph-based data structure and algorithms for circuit restructuring. Finally, we demonstrate a suboptimal circuit for which peephole optimization fails.

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The log files generated while operating a file system in disconnected mode grow to substantial sizes. Eliminating redundant or useless operations in these logs can free up scarce disk space on laptops, reduce replay times, and reduce the frequency of data conflict. Our approach uses a rule-based portable peephole optimizer for compilers. This suggests a general method of optimization for any system that performs logging at the vnode layer. 1. Introduction One goal of mobile computing is to provide users with a system that faithfully emulates the desktop environment. The mobile environment makes this goal a difficult one to reach because of limitations such as sporadic, low-bandwidth networks. Moreover, mobile computers tend to be resource poor, so that consumption of resources, such as disk space, demands careful control. The conventional paradigm for modern computing systems is distributed computing. An essential service in a distributed computing environment is the (distributed) fil...

Symbolic debuggers are system development tools that can accelerate the validation speed of behavioral specifications by allowing a user to interact with an executing code at the source level. In response to a user query, the debugger must be able to retrieve and display the value of a source variable in a manner consistent with what the user expects with respect to the source statement where execution has halted. However, when a behavioral specification has been optimized using transformations, values of variables may either be inaccessible in the run-time state or inconsistent with what the user expects. In this paper, we address the problem that pertains to the retrieval of source values for globally optimized behavioral specifications. We have developed a set of techniques that, given a behavioral specification CDFG, enforce computation of a selected subset Vcut of user variables such that (i) all other variables v 2 CDFG can be computed from Vcut and (ii) this enforcement has min...

Reversible logic circuit synthesis has applications in various modern computational problems, low power design, and quantum circuit synthesis. Several algorithms for synthesis and simplification of reversible logic have been proposed recently; however, they tend to be infeasible for circuits of more than a handful of inputs. In our work, we examine scalable methods to reduce the gate count of a given reversible circuit. Theoretical considerations we take up suggest that local optimization -- that is, the process of picking sub-optimal subcircuits, and replacing them with smaller counterparts -- may be a fruitful approach. In practice, our methods work well on circuits with up to 30 inputs, and find reductions in gate count as large as 35% in randomly generated circuits. We conclude with an example of a circuit for which local optimization fails, and further directions for research.

Model checking based on validating temporal logic formulas has proven practical and e#ective for numerous software engineering applications. As systems based on this approach have become more mainstream, a need has arisen to deal e#ectively with large batches of formulas over a common model. Presently, most systems validate formulas one at a time, with little or no interaction between validation of separate formulas. This is the case despite the fact that, for a wide range of applications, a certain level of redundancy between domain-related formulas can be anticipated.

In this report we study the e#ect of an optimizing algorithm for straight--line code which first constructs a directed acyclic graph representing the given program and then generates code from it. We show that this algorithm produces optimal code with respect to the classical transformations such as Constant Folding, Common Subexpression Elimination, and Dead Code Elimination. In contrast to the former, the latter are also applicable to iterative code containing loops. We can show that the graph--based algorithm essentially corresponds to a combination of the three classical optimizations in conjunction with Copy Propagation. Thus, apart from its theoretical importance, this result is relevant for practical compiler design as it allows to exploit the optimization potential of the graph--based algorithm for non--linear code as well. 1

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Several optimizations are easier to perform on SSA form, because SSA needs less analysis. Some optimizations can even be built into SSA construction. Advanced optimizations need advanced static analysis techniques on IR trees and SSA. In these lecture notes, we only deal with the SSA case