Results 1  10
of
150
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
Abstract

Cited by 109 (32 self)
 Add to MetaCart
(Show Context)
This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Some NPcomplete Geometric Problems
"... We show that the STEINER TREE problem and TRAVELING SALESMAN problem for points in the plane are NPcomplete when distances are measured either by the rectilinear (Manhattan) metric or by a natural discretized version of the Euclidean metric. Our proofs also indicate that the problems are NPhard i ..."
Abstract

Cited by 87 (1 self)
 Add to MetaCart
We show that the STEINER TREE problem and TRAVELING SALESMAN problem for points in the plane are NPcomplete when distances are measured either by the rectilinear (Manhattan) metric or by a natural discretized version of the Euclidean metric. Our proofs also indicate that the problems are NPhard if the distance I~asure is the (unmodified) Euclidean metric. However, for reasons we discuss, there is some question as to whether these problems, or even the wellsolved MINIMUM SPANNING TREE problem, are in NP when the distance measure is the Euclidean metric.
NearOptimal Critical Sink Routing Tree Constructions
, 1995
"... We present criticalsink routing tree (CSRT) constructions which exploit available criticalpath information to yield highperformance routing trees. Our CSSteiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at id ..."
Abstract

Cited by 55 (13 self)
 Add to MetaCart
We present criticalsink routing tree (CSRT) constructions which exploit available criticalpath information to yield highperformance routing trees. Our CSSteiner and "Global Slack Removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimizes Elmore delay directly, as opposed to heuristically abstracting linear or Elmore delay as in previous approaches. Extensive timing simulations on industry IC and MCM interconnect parameters show that our methods yield trees that significantly improve (by averages of up to 67%) over minimum Steiner routings in terms of delays to identified critical sinks. ERTs also serve as generic highperformance routing trees when no critical sink is specified: for 8sink nets in standard IC (MCM) technology, we improve average sink delay by 19% (62%) and maximum sink delay by 22% (52%) over the mini...
Optimally cutting a surface into a disk
 Discrete & Computational Geometry
, 2002
"... ..."
(Show Context)
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing
 IN PROC. DESIGN AUTOMATION CONF
, 1996
"... We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay tradeoff curve. We achieve this goal by limiting the solution space to the s ..."
Abstract

Cited by 50 (1 self)
 Add to MetaCart
We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay tradeoff curve. We achieve this goal by limiting the solution space to the set of topologies induced by a permutation on the sinks of the net. This constraint allows efficient identification of optimal solutions while still providing a rich solution space. Our approach also incorporates simultaneous wire sizing. Experimentally we have observed that routing topologies produced by previously proposed approaches consume up to 70% more area on average than topologies achieving equal or better delay produced by our algorithm. Our approach has also yielded improved minimum delay and has been adapted to improve a given routing topology for area minimization with good results.
Closing the Gap: NearOptimal Steiner Trees in Polynomial Time
 IEEE Trans. ComputerAided Design
, 1994
"... The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In ..."
Abstract

Cited by 43 (13 self)
 Add to MetaCart
(Show Context)
The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves nearlinear speedup on multiple processors. Several performanceimproving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multilayer routing. Motivated by the goal of reducing the running times of our algorith...
Efficient Algorithms for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design
"... Given an undirected graph G =(V;E) with positive edge weights (lengths) w: E!<+, a set of terminals (sinks) N V, and a unique root node r 2 N, a shortestpath Steiner arborescence (simply called an arborescence in the following) is a Steiner tree rooted at r spanning all terminals in N such thate ..."
Abstract

Cited by 39 (10 self)
 Add to MetaCart
Given an undirected graph G =(V;E) with positive edge weights (lengths) w: E!<+, a set of terminals (sinks) N V, and a unique root node r 2 N, a shortestpath Steiner arborescence (simply called an arborescence in the following) is a Steiner tree rooted at r spanning all terminals in N such thatevery sourcetosink path is a shortest path in G. Given a triple (G; N; r), the Minimum ShortestPath Steiner Arborescence (MSPSA) problem seeks an arborescence with minimum weight. The MSPSA problem has various applications in the areas of VLSI physical design, multicast network communication, and supercomputer message routing; various cases have been studied in the literature. In this paper, we propose several heuristics and exact algorithms for the MSPSA problem with applications to VLSI physical design. Experiments indicate that our
FastRoute: A step to integrate global routing into placement
 IEEE/ACM Intl. Conf. ComputerAided Design
, 2006
"... Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global rou ..."
Abstract

Cited by 32 (7 self)
 Add to MetaCart
(Show Context)
Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect information during the placement process, it is desirable to incorporate global routing into it. However, previous global routers are computationally expensive. It is impractical to perform global routing repeatedly during placement. In this paper, we present an extremely fast and highquality global router called FastRoute. In traditional global routing approaches, congestion is not considered during Steiner tree construction. So they have to rely on the timeconsuming maze routing technique to eliminate routing congestion. Different from traditional approaches, we proposed a congestiondriven Steiner tree topology generation technique and an edge shifting technique to determine the good Steiner tree topologies and Steiner node positions. Based on the congestiondriven Steiner trees, we only need to apply maze routing to a small percentage of the twopin nets once to obtain high quality global routing solutions. We also proposed a new cost function based on logistic function to direct the maze routing. Experimental results show that FastRoute generates less congested solutions in 132 × and 64 × faster runtimes than the stateoftheart academic global routers Labyrinth [1] and Chi Dispersion router [2], respectively. It is even faster than the highlyefficient congestion estimator FaDGloR [3]. The promising results make it possible to incorporate global routing directly into placement process without much runtime penalty. This could dramatically improve the placement solution quality. We believe this work will fundamentally change the way the EDA community look at and make use of global routing in the whole design flow. 1.
FLUTE: Fast Lookup Table Based Wirelength Estimation Technique
 In In Proceedings of the IEEE/ACM International Conference on ComputerAided Design
, 2004
"... Wirelength estimation is an important tool to guide the design optimization process in early design stages. In this paper, we present a novel wirelength estimation technique called FLUTE. Our technique is based on precomputed lookup table to make wirelength estimation very fast and very accurate fo ..."
Abstract

Cited by 31 (7 self)
 Add to MetaCart
(Show Context)
Wirelength estimation is an important tool to guide the design optimization process in early design stages. In this paper, we present a novel wirelength estimation technique called FLUTE. Our technique is based on precomputed lookup table to make wirelength estimation very fast and very accurate for low degree 1 nets. We show experimentally that for FLUTE, RMST, and HPWL, the average error in wirelength are 0.72%, 4.23%, and8.71%, respectively, and the normalized runtime are 1, 1.24, and 0.16, respectively. 1
A Survey on MultiNet Global Routing for Integrated Circuits
 Integration, the VLSI Journal
, 2001
"... This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential ..."
Abstract

Cited by 30 (4 self)
 Add to MetaCart
(Show Context)
This paper presents a comprehensive survey on global routing research over about the last two decades, with an emphasis on the problems of simultaneously routing multiple nets in VLSI circuits under various design styles. The survey begins with a coverage of traditional approaches such as sequential routing and ripupandreroute, and then discusses multicommodity flow based methods, which have attracted a good deal of attention recently. The family of hierarchical routing techniques and several of its variants are then overviewed, in addition to other techniques such as movebased heuristics and iterative deletion. While many traditional techniques focus on the conventional objective of managing congestion, newer objectives have come into play with the advances in VLSI technology. Specifically, the focus of global routing has shifted so that it is important to augment the congestion objective with metrics for timing and crosstalk. In the later part of this paper, we summarize the recent progress in these directions. Finally, the survey concludes with a summary of