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14
Improvements to Combinational Equivalence Checking
 In Proc. Int’l Conf. on ComputerAided Design
, 2006
"... The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). Stateoftheart methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), inte ..."
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Cited by 51 (20 self)
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The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). Stateoftheart methods use simulation and BDD/SAT sweeping on the input side (i.e. proving equivalence of some internal nodes in a topological order), interleaved with attempts to run SAT on the output (i.e. proving equivalence of the output to constant 0). This paper improves on this method by (a) using more intelligent simulation, (b) using CNFbased SAT with circuitbased decision heuristics, and (c) interleaving SAT with loweffort logic synthesis. Experimental results on public and industrial benchmarks demonstrate substantial reductions in runtime, compared to the current methods. In several cases, the new solver succeeded in solving previously unsolved problems. 1
Improvements to Technology Mapping for LUTbased FPGAs
 IEEE TCAD
, 2007
"... The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new t ..."
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Cited by 35 (12 self)
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The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new technique for onthefly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7% smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7 % and area by 14%, compared to DAOmap.
Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and MacroGates
, 2007
"... ... with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a small s ..."
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Cited by 7 (2 self)
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... with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a small set of logic functions that are able to implement a large portion of functions for given FPGA applications. Assuming that the extracted logic functions are implemented by macrogates in PLBs, we then develop a complete synthesis flow for such heterogeneous PLBs with mixed LUTs and macrogates. The flow includes a cutbased delay and area optimized technology mapping, a mixed binary integer and linear programming based area recovery algorithm to balance the resource utilization of macrogates and LUTs for areaefficient packing, and a SATbased packing. We finally evaluate the proposed heterogeneous FPGA using the newly developed flow and show that mixing LUT and macrogates, both with 6 inputs, improves performance by 16.5 % and reduces logic area by 30 % compared to using merely 6input LUTs.
Minimumperturbation retiming for delay optimization
 Proc. IWLS’10
"... This paper describes a fast retiming algorithm targeting delay while minimizing the number of flipflops moved. The algorithm can be applied before placement to minimize logic level, or after placement to minimize the critical region annotated with wire delays. Experiments on a suite of industrial b ..."
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Cited by 2 (2 self)
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This paper describes a fast retiming algorithm targeting delay while minimizing the number of flipflops moved. The algorithm can be applied before placement to minimize logic level, or after placement to minimize the critical region annotated with wire delays. Experiments on a suite of industrial benchmarks show that the algorithm improves fMAX by 9 % while increasing LUT count by 1 % and flipflop count by 2%, respectively. The runtime penalty is less than 1 % of the total runtime of the design flow. 1.
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate
, 2009
"... ... mixed with lookup tables (LUTs) inside programmable logic blocks (PLBs) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first develop a methodology to extract a small ..."
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Cited by 1 (0 self)
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... mixed with lookup tables (LUTs) inside programmable logic blocks (PLBs) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first develop a methodology to extract a small set logic functions that are able to implement a large portion of functions for given FPGA applications, and propose a heterogeneous PLB with one LUT and one macrogate for the selected logic functions. Furthermore, we develop a synthesis flow for such heterogeneous PLBs, including a cutbased delay and area optimized technology mapping, a mixed binary integer and linear programmingbased postmapping area recovery to balance the utilization of macrogates and LUTs, and a SATbased PLB architectureaware packing. Experiments using over 70 industrial benchmark applications show that we can extract four sixinput logic functions to cover more than 50 % functions of these applications, and the proposed synthesis flow reduces area by 5 % compared to an alternative flow without the postmapping area recovery when both have the optimal logic depth. Compared to the PLB with mixed LUT4 and small macrogates (XOR2 and MUX2), the PLB with mixed LUT4 and fourinput macrogate reduces logic depth by 6 % (and up to 42%) for the aforementioned applications.
Scalable sequential verification
, 2007
"... Abstract: In general, sequential verification is PSPACE complete, but for application to presentday industrial designs, it needs to be made scalable, which means essentially linear in circuit size. This paper focuses on the problem where the circuit in question has been transformed using a form of ..."
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Abstract: In general, sequential verification is PSPACE complete, but for application to presentday industrial designs, it needs to be made scalable, which means essentially linear in circuit size. This paper focuses on the problem where the circuit in question has been transformed using a form of scalable sequential synthesis. During this synthesis, a history AndInverterGraph (HAIG) is constructed, which efficiently records all logic nodes ever created in the synthesis process. A HAIG can be constructed in a fast, memory efficient, and scalable way. It is an FSM, which contains the initial and final FSMs to be compared as well as many redundant, sequentially equivalent nodes. The sets of equivalent nodes form “bridges ” connecting the initial and final machines and can be used to construct an inductive invariant. It is shown that this invariant is sufficient to prove delayed sequential equivalence between the two FSMs. The complexity of validating this is roughly the cost of one combinational SAT call of the size of the two machines; however, the many structural similarities, which are preidentified in the HAIG structure, make the proof of invariance particularly easy and scalable. 1
Abstract — Structural representation and technology mapping of
"... a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multilevel representation of binary networks, based on simple circuit structu ..."
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a Boolean function is an important problem in the design of nonregenerative digital logic circuits (also called combinational logic circuits). Library aware function manipulation offers a solution to this problem. Compact multilevel representation of binary networks, based on simple circuit structures, such as ANDInverter Graphs
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"... The disconnect between sequential synthesis and sequential verification has two consequences: (1) strong sequential optimizations are not used during synthesis because they are hard to verify, and (2) verification, if performed in isolation from synthesis, borders on becoming intractable. This paper ..."
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The disconnect between sequential synthesis and sequential verification has two consequences: (1) strong sequential optimizations are not used during synthesis because they are hard to verify, and (2) verification, if performed in isolation from synthesis, borders on becoming intractable. This paper develops a scalable methodology for checking sequential equivalence of the original network and the network derived by integrated sequential optimization [15]. The method uses an “optimization history” describing the sequence of logic transformations carried out during synthesis. A format for representing optimization history is proposed and motivated. A preliminary implementation of the proposed methodology is described and experimentally compared with an efficient generalpurpose equivalence checker that does not rely on information from synthesis. 1
A Dynamic AccuracyRefinement Approach to TimingDriven Technology Mapping
"... Abstract — Technology mapping aims at searching an optimal implementation for a Boolean netlist using gates from a technology library. Compared with its NPcomplete area minimization counterpart, DAG mapping for delay minimization is considered much sophisticated because matching choices must be m ..."
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Abstract — Technology mapping aims at searching an optimal implementation for a Boolean netlist using gates from a technology library. Compared with its NPcomplete area minimization counterpart, DAG mapping for delay minimization is considered much sophisticated because matching choices must be made without knowing actual arrival times and output loads. Traditional approaches to this problem involve too many approximate simplifications, and are far from accurate. In contrast, this paper tackles this problem directly under loaddependent DAG mapping. The enabling techniques for accurate optimization include onthefly loadestimation refinement, breadthfirst backward covering for load consolidation, and use of a piecewise linear model for accurate timing calculation. Experimental results show that, compared with the stateoftheart mapper, our method averagely reduces circuit delay by 39%, with 11 % increase in area, for large benchmark circuits. I.
Improvements to Technology Mapping for LUTBased
"... The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new ..."
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The paper presents several improvements to stateoftheart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improved cut enumeration computes all Kfeasible cuts without pruning for up to 7 inputs for the largest MCNC benchmarks. A new technique for onthefly cut dropping reduces by orders of magnitude memory needed to represent cuts for large designs. Improved area recovery leads to mappings with area on average 7 % smaller than DAOmap, while preserving delay optimality when starting from the same optimized netlists. Applying mapping with structural choices derived by a synthesis flow on average reduces delay by 7 % and area by 14%, compared to DAOmap.