This dissertation presents methods for automating the synthesis of embedded systems, i.e., special-purpose computers. In addition, it describes a method for analyzing the manner in which real-time operating system use influences embedded system power consumption.

Abstract — In order to effectively control nonlinear and multivariable models, and to incorporate constraints on system states, inputs and outputs (bounds, rate of change), a suitable (sometimes necessary) controller is Model Predictive Control (MPC). MPC is an optimization-based control scheme that requires abundant matrix operations for the calculation of the optimal control moves. In this work we propose a mixed software and hardware embedded MPC implementation. Using a codesign step and based on profiling results, we decompose the optimization algorithm into two parts: one that fits into a host processor and one that fits into a custom made unit, that performs the computationally demanding arithmetic operations. The profiling results and information on the coprocessor design are provided. I.

In hardware/software codesign, modeling is a very important issue. The model must capture the features of the system and describe its functionality. The design cycle must be based on formal representations so that the synthesis of a design from specification to implementation can be carried out systematically. Many models have been proposed for representing HW/SW systems. This report is the result of a survey on hardware/software codesign representation models. It relates the characteristics of several existing models and compares their properties. This work is encompassed in the SAVE project, which aims to study the specification and verification of heterogeneous electronic systems. The main objective of this survey is to explore the field of modeling of heterogeneous systems.

The methodologies that are in use today for software development rely on representations and techniques appropriate for the applications (compilers, business applications, CAD, etc.) that have been traditionally implemented on programmable processors. Embedded software is different: by virtue of being embedded in a surrounding system, the software must be able to continuously react to stimula in the desired way. Verifying the correctness of the system requires that the model of the software be transformed to include (refine) or exclude (abstract) information to retain only what is relevant to the task at hand. In this paper, we outline a framework that weinted to use for studying the problems of abstraction and refinement in the context of embedded software for hybrid systems.

WeintroduceSIDE(theacronymstandsforSensors InaDistributedEnvironment)---asoftwarepackage fordevelopingcontrolprogramsforreactivesystems. OnedistinctivefeatureofSIDEisthatitcanbeused asasimulator:some(orevenall)componentsofthe underlyingphysicalnetworkcanbevirtual.Notably, thecontrolprogramitselfneednotbeawarethat somepartsofitsenvironmentarenotreal.SIDE applicationscanbenaturallydistributedandinterconnectedviatheInternet. 1

This paper presents MODEST (MOdeling and DEscription language for Stochastic Timed systems), a formalism that is aimed to support (i) the modular description of reactive system’s behaviour while covering both (ii) functional and (iii) non-functional system aspects such as timing and quality-ofservice constraints in a single specification. The language contains features such as simple and structured data types, structuring mechanisms like parallel composition and abstraction, means to control the granularity of assignments, exception handling, and non-deterministic and random branching and timing. MODEST can be viewed as an overarching notation for a wide spectrum of models, ranging from labeled transition systems, to timed automata (and probabilistic variants thereof) as well as prominent stochastic processes such as (generalized semi-)Markov chains and decision processes. The paper describes the design rationales and details of the syntax and semantics.

This paper focuses on the problem of enabling system companies to quickly integrate IPs from different sources, and adapt them to different manufacturing technologies. An evolutionary approach from current methodologies is possible with appropriate and extensive CAD support. We cover the main aspects of interfacing Intellectual Property, both in hardware and software form, in an embedded system design context. In particular, we review the main approaches to specification, synthesis and validation of interfaces that have appeared in the literature. From the specification viewpoint, we illustrate the main protocol and timing constraint specification models. From the synthesis and optimization viewpoint, we review software and hardware generation, as well as time-driven interface scheduling techniques. From the verification viewpoint, we discuss various strategies for hardware/software co-simulation, with special attention to the interface layer. Finally, we consider the growing importanc...

Hardware/software codesign involves various design problems including system specification, design space exploration, hardware/software co-verification, and system synthesis. A codesign environment is a software tool that facilitates capabilities to solve these design problems. This paper presents the PeaCE codesign environment mainly targeting for multimedia applications with real-time constraints. PeaCE specifies the system behavior with a heterogeneous composition of three models of computation. The PeaCE environment provides seamless co-design flow from functional simulation to system synthesis, utilizing the features of the formal models maximally during the whole design process. Preliminary experiments with real examples prove the viability of the proposed technique. 1.

Growing design complexity has made functional debugging of application-specific integrated circuits crucial to their development. Two widely used debugging techniques are simulation and emulation. Design simulation provides good controllability and observability of the variables in a design, but is two to ten orders of magnitude slower than the fabricated design. Design emulation and fabrication provide high execution speed, but significantly restrict design observability and controllability. To facilitate debugging, and in particular error diagnosis, we introduce a novel cut-based functional debugging paradigm that leverages the advantages of both emulation and simulation. The approach enables the user to run long test sequences in emulation, and upon error detection, roll-back to an arbitrary instance in execution time, and transparently switch over to simulation-based debugging for full design visibility and controllability. The new debugging approach introduces several optimization problems. We formulate the optimization tasks, establish their complexity, and develop most-constrained least-constraining heuristics to solve them. The effectiveness of the new approach and accompanying algorithms is demonstrated on a set of benchmark designs where combined emulation and simulation is enabled with low hardware overhead.

In the last decade, electronic systems have become increasingly complex. The number of func-tionalities built on one chip have risen enormously. To solve the problem of cost and flexibility for such sophisticated, systems the usage of mixed hardware software systems has increased. Due to the complexity, the system development has become more and more difficult and the simulation and evaluation has become a key position of the design process. Many tools which aid designers in the evaluation of electronic systems have been developed. However, un-til recently, tools for the simulation of mixed HW/SW systems have been lacking. An early ap-proach to HW/SW co-design and cosimulation was presented by the University of California, Berkeley [8] in 1991 within their system design project Ptolemy. During the last years some vendors have begun offering tools to close this gap. In 1996, Mentor Graphics presented Seamless, a cosimulation tool that supports as a backplane the con-nection between the software execution and the hardware simulator. Competing products are EagleI and EagleV, which have been developed concurrently by Eagle Design Automation